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vhdl_verification
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Examples and design pattern for VHDL verification
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vhdl_verification/psl_test_endpoint/psl_test_endpoint.tcl

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Initial commit of PSL endpoint test design
8 years ago
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  1. set signals [list]
  2. lappend signals "top.psl_test_endpoint.s_rst_n"
  3. lappend signals "top.psl_test_endpoint.s_clk"
  4. lappend signals "top.psl_test_endpoint.s_write"
  5. lappend signals "top.psl_test_endpoint.s_read"
  6. set num_added [ gtkwave::addSignalsFromList $signals ]