From c48ea0f28890c1d44301f6bc7a2d1912c494c31b Mon Sep 17 00:00:00 2001 From: tmeissner Date: Sun, 3 Apr 2016 15:38:24 +0200 Subject: [PATCH] Add writing psl endpoint value into VHDL boolean signal --- .../psl_endpoint_eval_in_vhdl.vhd | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/psl_endpoint_eval_in_vhdl/psl_endpoint_eval_in_vhdl.vhd b/psl_endpoint_eval_in_vhdl/psl_endpoint_eval_in_vhdl.vhd index e37ff4c..b223c43 100644 --- a/psl_endpoint_eval_in_vhdl/psl_endpoint_eval_in_vhdl.vhd +++ b/psl_endpoint_eval_in_vhdl/psl_endpoint_eval_in_vhdl.vhd @@ -19,6 +19,7 @@ architecture test of psl_endpoint_eval_in_vhdl is signal s_clk : std_logic := '0'; signal s_write : std_logic; signal s_read : std_logic; + signal s_test0 : boolean; begin @@ -59,4 +60,15 @@ begin end process; -end architecture test; \ No newline at end of file + process is + begin + wait until rising_edge(s_clk); + if (E_TEST0) then + s_test0 <= true; + else + s_test0 <= false; + end if; + end process; + + +end architecture test;