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vhdl_verification
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Examples and design pattern for VHDL verification
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vhdl_verification/osvvm_fsm_coverage/osvvm_fsm_coverage.tcl

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set signals [list]
lappend signals "top.osvvm_fsm_coverage.s_reset_n"
lappend signals "top.osvvm_fsm_coverage.s_clk"
lappend signals "top.osvvm_fsm_coverage.s_fsm_state"
set num_added [ gtkwave::addSignalsFromList $signals ]