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60 lines
1.1 KiB
60 lines
1.1 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library std;
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use std.env.all;
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entity psl_test_endpoint is
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end entity psl_test_endpoint;
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architecture test of psl_test_endpoint is
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signal s_rst_n : std_logic := '0';
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signal s_clk : std_logic := '0';
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signal s_write : std_logic;
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signal s_read : std_logic;
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begin
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s_rst_n <= '1' after 100 ns;
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s_clk <= not s_clk after 10 ns;
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TestP : process is
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begin
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report "RUNNING psl_test_endpoint test case";
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report "==========================================";
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s_write <= '0'; -- named assertion should hit
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s_read <= '0';
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wait until s_rst_n = '1' and rising_edge(s_clk);
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s_write <= '1';
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wait until rising_edge(s_clk);
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s_read <= '1'; -- assertion should hit
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wait until rising_edge(s_clk);
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s_write <= '0';
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s_read <= '0';
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wait until rising_edge(s_clk);
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stop(0);
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wait;
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end process TestP;
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-- psl default clock is rising_edge(s_clk);
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-- psl endpoint E_TEST0 is {not(s_write); s_write};
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process is
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begin
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wait until E_TEST0;
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report "HIT";
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wait;
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end process;
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end architecture test;
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