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@ -24,10 +24,12 @@ end entity alu; |
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architecture rtl of alu is |
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constant c_add : std_logic_vector(1 downto 0) := "00"; |
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constant c_sub : std_logic_vector(1 downto 0) := "01"; |
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constant c_and : std_logic_vector(1 downto 0) := "10"; |
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constant c_or : std_logic_vector(1 downto 0) := "11"; |
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subtype t_opc is std_logic_vector(Opc_i'length-1 downto 0); |
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constant c_add : t_opc := "00"; |
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constant c_sub : t_opc := "01"; |
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constant c_and : t_opc := "10"; |
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constant c_or : t_opc := "11"; |
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begin |
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@ -40,14 +42,14 @@ begin |
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elsif (rising_edge(Clk_i)) then |
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case Opc_i is |
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when c_add => (OverFlow_o, Dout_o) <= |
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std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) + |
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resize(unsigned(DinB_i), Dout_o'length+1)); |
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std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) + |
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resize(unsigned(DinB_i), Dout_o'length+1)); |
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when c_sub => (OverFlow_o, Dout_o) <= |
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std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) - |
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resize(unsigned(DinB_i), Dout_o'length+1)); |
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when c_and => Dout_o <= DinA_i and DinB_i; |
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when c_or => Dout_o <= DinA_i or DinB_i; |
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when others => null; |
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std_logic_vector(resize(unsigned(DinA_i), Dout_o'length+1) - |
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resize(unsigned(DinB_i), Dout_o'length+1)); |
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when c_and => Dout_o <= DinA_i and DinB_i; |
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when c_or => Dout_o <= DinA_i or DinB_i; |
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when others => null; |
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end case; |
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end if; |
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end process; |
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