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@ -100,7 +100,7 @@ begin |
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when GET_DATA => |
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if (unsigned(a_addr) <= 7) then |
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-- s_data <= s_register(to_integer(unsigned(a_addr))); |
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s_data <= s_register(to_integer(unsigned(a_addr))); |
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else |
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s_error <= true; |
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s_data <= (others => '0'); |
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@ -112,7 +112,7 @@ begin |
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DinAccept_o <= '0'; |
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if (DinStop_i = '1') then |
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if (unsigned(a_addr) <= 7) then |
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-- s_register(to_integer(unsigned(a_addr))) <= Din_i; |
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s_register(to_integer(unsigned(a_addr))) <= Din_i; |
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else |
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s_error <= true; |
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end if; |
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@ -165,11 +165,12 @@ begin |
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FormalG : if Formal generate |
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signal s_addr : natural range 0 to 15; |
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type t_cmd is (READ, WRITE, NOP); |
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signal s_cmd : t_cmd; |
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type t_vai is record |
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Start : std_logic; |
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Stop : std_logic; |
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@ -177,13 +178,14 @@ begin |
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Valid : std_logic; |
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Accept : std_logic; |
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end record t_vai; |
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signal s_job_req : t_vai; |
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signal s_job_ack : t_vai; |
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begin |
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-- VHDL helper logic |
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process is |
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begin |
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@ -200,8 +202,8 @@ begin |
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end if; |
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end process; |
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default clock is rising_edge(Clk_i); |
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default clock is rising_edge(Clk_i); |
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-- RESTRICTIONS |
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@ -210,7 +212,7 @@ begin |
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-- CONSTRAINTS |
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-- Valid stable until accepted |
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JOB_REQ_VALID_STABLE : assume always |
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DinValid_i and not DinAccept_o -> next (DinValid_i until_ DinAccept_o); |
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@ -218,11 +220,11 @@ begin |
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-- Start stable until accepted |
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JOB_REQ_START_STABLE : assume always |
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DinValid_i and not DinAccept_o -> next (DinStart_i = s_job_req.Start until_ DinAccept_o); |
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-- Stop stable until accepted |
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JOB_REQ_STOP_STABLE : assume always |
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DinValid_i and not DinAccept_o -> next (DinStop_i = s_job_req.Stop until_ DinAccept_o); |
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-- Data stable until accepted |
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JOB_REQ_DIN_STABLE : assume always |
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DinValid_i and not DinAccept_o -> next (Din_i = s_job_req.Data until_ DinAccept_o); |
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@ -230,6 +232,17 @@ begin |
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-- ASSERTIONS |
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-- Reset values |
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AFTER_RESET : assert always |
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not Reset_n_i |
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-> |
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s_fsm_state = IDLE and |
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not DinAccept_o and |
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not DoutStart_o and |
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not DoutStop_o and |
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not DoutValid_o and |
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s_register = (0 to 7 => x"00"); |
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-- FSM states in valid range |
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FSM_STATES_VALID : assert always |
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s_fsm_state = IDLE or s_fsm_state = GET_HEADER or |
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@ -262,34 +275,34 @@ begin |
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-- a job read acknowledge has to follow |
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READ_VALID_ACK : assert always |
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{s_fsm_state = GET_HEADER and DinValid_i = '1' and DinStart_i = '1' and |
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Din_i(3 downto 0) = x"0" and DinStop_i = '1'} |
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Din_i(3 downto 0) = x"0" and DinStop_i = '1'} |
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|=> |
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{-- Job ack header cycle |
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(not DoutValid_o)[*]; |
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(DoutValid_o and DoutStart_o and not DoutAccept_i)[*]; |
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(DoutValid_o and DoutStart_o and DoutAccept_i); |
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not DoutValid_o [*]; |
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DoutValid_o and DoutStart_o and not DoutAccept_i [*]; |
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DoutValid_o and DoutStart_o and DoutAccept_i; |
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-- Job ack data cycle |
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(not DoutValid_o)[*]; |
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(DoutValid_o and not DoutStart_o and not DoutStop_o and not DoutAccept_i)[*]; |
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(DoutValid_o and not DoutStart_o and not DoutStop_o and DoutAccept_i); |
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not DoutValid_o [*]; |
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DoutValid_o and not DoutStart_o and not DoutStop_o and not DoutAccept_i [*]; |
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DoutValid_o and not DoutStart_o and not DoutStop_o and DoutAccept_i; |
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-- Job ack footer cycle |
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(not DoutValid_o)[*]; |
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not DoutValid_o [*]; |
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DoutValid_o and DoutStop_o}; |
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-- After a valid job write request, |
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-- a job read acknowledge has to follow |
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WRITE_VALID_ACK : assert always |
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{s_fsm_state = GET_HEADER and DinValid_i = '1' and DinStart_i = '1' and |
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Din_i(3 downto 0) = x"1" and DinStop_i = '0'; |
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(not DinValid_i)[*]; |
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DinValid_i and DinStop_i} |
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Din_i(3 downto 0) = x"1" and DinStop_i = '0'; |
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not DinValid_i [*]; |
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DinValid_i and DinStop_i} |
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|=> |
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{-- Job ack header cycle |
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(not DoutValid_o)[*]; |
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(DoutValid_o and DoutStart_o and not DoutAccept_i)[*]; |
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(DoutValid_o and DoutStart_o and DoutAccept_i); |
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not DoutValid_o [*]; |
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DoutValid_o and DoutStart_o and not DoutAccept_i [*]; |
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DoutValid_o and DoutStart_o and DoutAccept_i; |
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-- Job ack footer cycle |
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(not DoutValid_o)[*]; |
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not DoutValid_o [*]; |
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DoutValid_o and DoutStop_o}; |
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-- Start & stop flag have to be exclusive |
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@ -316,9 +329,30 @@ begin |
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JOB_ACK_DOUT_STABLE : assert always |
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DoutValid_o and not DoutAccept_i -> next (Dout_o = s_job_ack.Data until_ DoutAccept_i); |
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-- READ_DATA : assert always |
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-- (DoutValid_o and not DoutStart_o and not DoutStop_o) -> |
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-- (Dout_o = s_register(to_integer(unsigned(a_addr)))); |
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-- Data from selected address has to be read |
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READ_DATA : assert always |
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DoutValid_o and not DoutStart_o and not DoutStop_o and s_addr <= 7 |
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-> |
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Dout_o = s_register(s_addr); |
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-- 0 has to be read when invalid address is given |
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READ_DATA_INV_ADDR : assert always |
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DoutValid_o and not DoutStart_o and not DoutStop_o and s_addr > 7 |
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-> |
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Dout_o = x"00"; |
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-- Register has to be written at given address with given data |
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-- when correct job req write occurs |
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WRITE_DATA : assert always |
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-- Job req header cycle |
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{s_fsm_state = GET_HEADER and DinValid_i = '1' and DinStart_i = '1' and |
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Din_i(3 downto 0) = x"1" and unsigned(Din_i(7 downto 4)) <= 7 and DinStop_i = '0'; |
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-- Job req data / footer cycle |
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not DinValid_i [*]; |
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DinValid_i and not DinStart_i and DinStop_i and not DinAccept_o [*]; |
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DinValid_i and not DinStart_i and DinStop_i and DinAccept_o} |
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|=> |
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{s_register(s_addr) = s_job_req.Data}; |
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-- FUNCTIONAL COVERAGE |
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@ -326,6 +360,7 @@ begin |
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FOOTER_VALID : cover {DoutValid_o = '1' and DoutStop_o = '1' and Dout_o = 8x"0"}; |
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FOOTER_ERR : cover {DoutValid_o = '1' and DoutStop_o = '1' and Dout_o = 8x"1"}; |
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end generate FormalG; |
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