Trying to verify Verilog/VHDL designs with formal methods and tools
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[tasks]
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cover
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bmc
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prove
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[options]
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depth 25
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cover: mode cover
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bmc: mode bmc
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prove: mode prove
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[engines]
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cover: smtbmc z3
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bmc: abc bmc3
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prove: abc pdr
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[script]
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ghdl --std=08 -gFormal=true -gDepth=16 -gWidth=16 fifo.vhd fwft_fifo.vhd -e fwft_fifo
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prep -top fwft_fifo
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# Convert all assumes to asserts in sub-units
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chformal -assume2assert fwft_fifo/* %M
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# Remove selected covers in i_fifo sub-unit as they cannot be reached
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chformal -cover -remove */formalg.read_pnt_stable_when_empty.cover
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chformal -cover -remove */formalg.rerror.cover
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[files]
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../fifo/fifo.vhd
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fwft_fifo.vhd
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