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682 B

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TestDesign is
port (
clk : in std_logic;
resetn : in std_logic;
sel : in std_logic_vector(1 downto 0);
we : out std_logic_vector(3 downto 0)
);
end entity TestDesign;
architecture rtl of TestDesign is
begin
process (CLK, RESETn) is
begin
if (RESETn = '0') then
we <= (others => '0');
elsif (rising_edge(CLK)) then
we(0) <= '0' when sel = "00" else '1';
we(1) <= '0' when sel = "01" else '1';
we(2) <= '0' when sel = "10" else '1';
we(3) <= '0' when sel = "11" else '1';
end if;
end process;
end architecture;