Updated 18 hours ago

Trying to verify Verilog/VHDL designs with formal methods and tools

Updated 1 day ago

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

Updated 2 days ago

cryptography ip-cores in vhdl / verilog

Updated 6 days ago

Exercises & activities from the go workshop provided by Packt: https://courses.packtpub.com/courses/go

Updated 5 months ago

Library of reusable VHDL components

Updated 5 months ago

Various Arduino related stuff

Updated 6 months ago

Web page of meissner-wohnen.de

Updated 8 months ago

(Somewhat adapted) code and solutions from the book "Build Your Own Lisp"

Updated 1 year ago

Updated 1 year ago

Updated 2 years ago

openSCAD models for 3d-printing

Updated 2 years ago

Examples and design pattern for VHDL verification

Updated 2 years ago

Tutorials from Pebble developer website

Updated 2 years ago

Updated 2 years ago

usb-avr-cpld experiment board with FTDI FT232RL, ATMEGA88 & XC9572XL

Updated 2 years ago

Updated 2 years ago

Some experiments with web applications

Updated 2 years ago

Various projects using Raspberry Pi

Updated 2 years ago

Learning by doing: Reading books and trying to understand the (code) examples

Updated 2 years ago