You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
T. Meissner 10ce6d9d74 Add GHA workflow for simulation of VHDL design 7 months ago
.github/workflows Add GHA workflow for simulation of VHDL design 7 months ago
tlv Final RISC-V code in TL-Verilog 7 months ago
vhdl Add synthesis target 7 months ago
README.md Add GHA workflow for simulation of VHDL design 7 months ago

README.md

tests

The original repository is located on my own git-server at https://git.goodcleanfun.de/tmeissner/lfd111x_building_a_risc-v-cpu_core

It is mirrored to github with every push, so both should be in sync.

lfd111x_building_a_risc-v-cpu_core

Code from the Linux Foundation course Building a RISC-V CPU Core at edX. I have added VHDL implementations equivalent to the TL-Verilog ones.