|T. Meissner 10ce6d9d74||7 months ago|
|.github/workflows||7 months ago|
|tlv||7 months ago|
|vhdl||7 months ago|
|README.md||7 months ago|
The original repository is located on my own git-server at https://git.goodcleanfun.de/tmeissner/lfd111x_building_a_risc-v-cpu_core
It is mirrored to github with every push, so both should be in sync.
Code from the Linux Foundation course Building a RISC-V CPU Core at edX. I have added VHDL implementations equivalent to the TL-Verilog ones.