tmeissner
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lfd111x_building_a_risc-v-cpu_core
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10 Commits (master)
 

Author SHA1 Message Date
  T. Meissner 10ce6d9d74 Add GHA workflow for simulation of VHDL design 4 years ago
  T. Meissner 5cdb309c88 Add synthesis target 4 years ago
  T. Meissner 49574bbbf0 Update VHDL code to ne equivalent to final tlv version 4 years ago
  T. Meissner dcfd562278 Add data memory 4 years ago
  T. Meissner 7dd99caa6f Update instr memory content to fimal program 4 years ago
  T. Meissner d52e1681b9 Add decoding of remaining instr; move instr mem into pkg; add jump logic; Makefile refactoring 4 years ago
  T. Meissner 03b2872c8d Final RISC-V code in TL-Verilog 4 years ago
  T. Meissner 83ac343f65 Add readme 4 years ago
  T. Meissner 6954c706cd Add VHDL impl. equivalent to tlv version 4 years ago
  T. Meissner 306c34abb5 Initial commit, version after ch. 4: risc-v subset cpu 4 years ago