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lfd111x_building_a_risc-v-cpu_core
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Commit Graph

  • 10ce6d9 (HEAD -> master) Add GHA workflow for simulation of VHDL design by tmeissner 2021-03-20 01:32:43 +0100
  • 5cdb309 Add synthesis target by tmeissner 2021-03-20 01:26:30 +0100
  • 49574bb Update VHDL code to ne equivalent to final tlv version by tmeissner 2021-03-20 01:25:23 +0100
  • dcfd562 Add data memory by tmeissner 2021-03-19 20:44:34 +0100
  • 7dd99ca Update instr memory content to fimal program by tmeissner 2021-03-19 20:28:28 +0100
  • d52e168 Add decoding of remaining instr; move instr mem into pkg; add jump logic; Makefile refactoring by tmeissner 2021-03-19 19:07:50 +0100
  • 03b2872 Final RISC-V code in TL-Verilog by tmeissner 2021-03-19 18:45:01 +0100
  • 83ac343 (tag: chapter_4) Add readme by tmeissner 2021-03-14 02:04:38 +0100
  • 6954c70 Add VHDL impl. equivalent to tlv version by tmeissner 2021-03-14 01:47:33 +0100
  • 306c34a Initial commit, version after ch. 4: risc-v subset cpu by tmeissner 2021-03-13 21:43:07 +0100