cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
T. Meissner 81df6e0215 Update & restructure DES testbench to use openSSL and random simuli 2 weeks ago
.github ci: update test script 1 month ago
aes aes: fix build arg order 1 month ago
cbcdes Update CBCDES unit and tests 6 months ago
cbcmac_aes Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 6 months ago
cbcmac_des Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 6 months ago
cbctdes Add Makefile for synthesis of CBCTDES 1 month ago
ctraes Fix CTR-init round, set of iv & key in 1st round only. 1 month ago
des Update & restructure DES testbench to use openSSL and random simuli 2 weeks ago
lib Add OSVVM as submodule 6 months ago
tdes Minor update to TDES sim makefile and testbench 1 month ago
.gitignore added ignore file 7 years ago
.gitmodules Add OSVVM as submodule 6 months ago
LICENSE.textile added GPLv2 license file 5 years ago
README.md Update CI-badge; add hint to VHPIdirect use in *aes testbenches 1 month ago

README.md

simulation

cryptocores

Cryptography IP-cores & tests written in VHDL / Verilog

The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.

The testbenches to verify AES and CTR-AES are examples how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness of the VHDL implementation.

HINT:

The tests of some algorithms use the OSVVM library, which is redistributed as submodule. To get & initialize the submodule, please use the --recursive option when cloning this repository.