cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
T. Meissner 5640e7884b Update CBCDES unit and tests 4 months ago
aes Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 months ago
cbcdes Update CBCDES unit and tests 4 months ago
cbcmac_aes Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 months ago
cbcmac_des Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 months ago
cbctdes removed internal synced copy of reset_i; set ready to high in reset 6 years ago
ctraes Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 months ago
des Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 months ago
lib Add OSVVM as submodule 4 months ago
tdes Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 months ago
.gitignore added ignore file 7 years ago
.gitmodules Add OSVVM as submodule 4 months ago
LICENSE.textile added GPLv2 license file 5 years ago
README.md Use co-sim with openSSL to check AES enc VHDL implementation 4 months ago

README.md

cryptocores

cryptography ip-cores in vhdl / verilog

The components in this repository are not intended for productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.

HINT:

The tests of some algorithms use the OSVVM library, which is redistributed as submodule. To get & initialize the submodule, please use the --recursive option when cloning this repository.