cryptography ip-cores in vhdl / verilog
vhdl
osvvm
fpga
ghdl
testbenches
verilog

README.md 348B

cryptocores

cryptography ip-cores in vhdl / verilog

The components in this repository are not intended for productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.