223 Commits (master)
 

Author SHA1 Message Date
  T. Meissner 302ad79ced Add CBC-AES testbench using VHPIdirect & openSSL as reference 4 months ago
  T. Meissner 3de7dd63a9 Add CBC-AES VHDL design & synthesis Makefile 4 months ago
  T. Meissner 2a3fae594f Refactor conditions in counter process; add info about submodule update 4 months ago
  T. Meissner 29668c3214 Bump OSVVM to version 2020.12a 4 months ago
  T. Meissner 81df6e0215 Update & restructure DES testbench to use openSSL and random simuli 5 months ago
  T. Meissner b602931174 Fix CTR-init round, set of iv & key in 1st round only. 6 months ago
  T. Meissner 4c3aa07711 Update CTR-AES testbench to use openSSL as reference, unpolished 7 months ago
  T. Meissner 250fbf34b3 Update CI-badge; add hint to VHPIdirect use in *aes testbenches 7 months ago
  T. Meissner 1fdbcb2d5f
Merge pull request #2 from umarcor/ci/update 7 months ago
  umarcor 24bee6a79b ci: update test script 7 months ago
  umarcor 2e20cf9400 ci: add icons/emojis 7 months ago
  umarcor 7835fc5204 readme: use shield/badge from shields.io 7 months ago
  umarcor 17ce27949f ci: rename 'test' workflow to 'Simulation' 7 months ago
  T. Meissner d9d91763bb CTR-AES: Fix counter incr & init; add 1st simple testbench 7 months ago
  T. Meissner 2d708cbb51 Minor update to TDES sim makefile and testbench 7 months ago
  T. Meissner e3e993fe4b Add Makefile for synthesis of CBCTDES 7 months ago
  T. Meissner 7540c3d2bf Add GHA badge 7 months ago
  T. Meissner e9f14349e6
Merge pull request #1 from umarcor/ci/gha 7 months ago
  umarcor d7b39f322e ci: add GitHub Actions workflow 'test' 7 months ago
  umarcor 6ebfd4afe7 aes: fix build arg order 7 months ago
  umarcor 325a08f301 aes: fix VHDL sources order 7 months ago
  T. Meissner 5640e7884b Update CBCDES unit and tests 11 months ago
  T. Meissner a2c530928e Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 11 months ago
  T. Meissner 1850e5c1e3 Add Makefiles for VHDL synthesis of DES & TDES 11 months ago
  T. Meissner 2e48c18741 Some Makefile refactoring 11 months ago
  T. Meissner cc268c2efb Fix osvvm path 11 months ago
  T. Meissner c5a7007ac5 Implement key schedule for AES decryption, unoptimized 11 months ago
  T. Meissner 1dc2fd2458 Use co-sim for descryption tests also 11 months ago
  T. Meissner 51d7b485b9 Make PSL compatible with simulation & synthesis 11 months ago
  T. Meissner 0a7ed338d6 Use co-sim with openSSL to check AES enc VHDL implementation 11 months ago
  T. Meissner d16c247b5c Add OSVVM as submodule 11 months ago
  T. Meissner 491b4df54f Move PSL stuff in generate block; add formal PSL code 11 months ago
  T. Meissner 303bda25e4 Add CTR-AES VHDL design 11 months ago
  T. Meissner dce8396498 Refactoring; remove unused functions 11 months ago
  T. Meissner 50aaca8c6c Fix PSL cover directives 11 months ago
  T. Meissner b7b9f36c9b Add CBCMAC-AES VHDL design 11 months ago
  T. Meissner 28b2cd3856 Implement key schedule for encryption, finally 11 months ago
  T. Meissner b59791e8f3 Move VHDL library files in work directory 2 years ago
  T. Meissner 77f87536c9 FSM optimizations; PSL enhancements 2 years ago
  T. Meissner c400d2ef1b Add PSL checkers, refactoring 2 years ago
  T. Meissner 735c411ff8 First working version of AES enc & dec 2 years ago
  T. Meissner d8ca919f37 Fixed many incorrect implemented functions 2 years ago
  T. Meissner 42a5eb9b1b Minor refactoring & bugfixing 2 years ago
  T. Meissner 27e06dff2c Fix gmul() & (inv)mixcolums() functions 2 years ago
  T. Meissner 517237cfec Created Readme.md file 5 years ago
  T. Meissner 2f91130184 Add remaining AES functions 6 years ago
  T. Meissner 46f1b9295b merge last changes from amc mini repo 6 years ago
  T. Meissner 8a9b30940e integrate s1-s8() into one s() function with additional parameter s_table; convert lower to upper case 6 years ago
  T. Meissner 313a08b6f3 add verilog simulation environment for cbcmac-des 6 years ago
  T. Meissner 4dd3f74d15 Merge branch 'master' of https://github.com/tmeissner/cryptocores 6 years ago