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add verilog simulation environment for cbcmac-des

T. Meissner 4 years ago
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313a08b6f3

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cbcmac_des/sim/verilog/data_input.txt View File

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+3736353433323120
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+4e6f772069732074
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+68652074696d6520
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+666f722000000000

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cbcmac_des/sim/verilog/data_output.txt View File

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+21fb193693a16c28
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+6c463f0cb7167a6f
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+956ee891e889d91e
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+f1d30f6849312ca4

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cbcmac_des/sim/verilog/makefile View File

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+# ======================================================================
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+# DES encryption/decryption
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+# algorithm according to FIPS 46-3 specification
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+# Copyright (C) 2012 Torsten Meissner
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+#-----------------------------------------------------------------------
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+# This program is free software; you can redistribute it and/or modify
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+# it under the terms of the GNU General Public License as published by
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+# the Free Software Foundation; either version 2 of the License, or
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+# (at your option) any later version.
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+
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+# This program is distributed in the hope that it will be useful,
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+# but WITHOUT ANY WARRANTY; without even the implied warranty of
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+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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+# GNU General Public License for more details.
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+
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+# You should have received a copy of the GNU General Public License
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+# along with this program; if not, write to the Free Software
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+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
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+# ======================================================================
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+
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+
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+SRC_FILES = tb_cbcmac_des.v ../../rtl/verilog/cbcmac_des.v ../../../des/rtl/verilog/des.v
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+SIM_FILES = data_input.txt data_output.txt
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+
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+.PHONY: all
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+all : sim wave
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+
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+.PHONY: sim
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+sim : tb_cbcmac_des.vcd
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+
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+tb_cbcmac_des.vcd : $(SRC_FILES) $(SIM_FILES)
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+	iverilog -Wall -s tb_cbcmac_des -o tb_cbcmac_des $(SRC_FILES)
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+	vvp tb_cbcmac_des
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+
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+.PHONY: wave
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+wave : tb_cbcmac_des.vcd
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+	gtkwave -S tb_cbcmac_des.tcl tb_cbcmac_des.vcd &
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+
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+.PHONY: clean
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+clean :
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+	echo "# cleaning simulation files"
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+	rm -f tb_cbcmac_des
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+	rm -f tb_cbcmac_des.vcd

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cbcmac_des/sim/verilog/tb_cbcmac_des.tcl View File

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+set signals [list]
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+lappend signals "tb_cbcmac_des.reset"
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+lappend signals "tb_cbcmac_des.clk"
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+lappend signals "tb_cbcmac_des.validin"
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+lappend signals "tb_cbcmac_des.acceptout"
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+lappend signals "tb_cbcmac_des.start"
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+lappend signals "tb_cbcmac_des.key"
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+lappend signals "tb_cbcmac_des.datain"
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+lappend signals "tb_cbcmac_des.validout"
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+lappend signals "tb_cbcmac_des.acceptin"
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+lappend signals "tb_cbcmac_des.dataout"
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+set num_added [ gtkwave::addSignalsFromList $signals ]

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cbcmac_des/sim/verilog/tb_cbcmac_des.v View File

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+// ======================================================================
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+// DES encryption/decryption testbench
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+// tests according to NIST 800-17 special publication
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+// Copyright (C) 2012 Torsten Meissner
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+//-----------------------------------------------------------------------
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+// This program is free software; you can redistribute it and/or modify
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+// it under the terms of the GNU General Public License as published by
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+// the Free Software Foundation; either version 2 of the License, or
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+// (at your option) any later version.
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+//
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+// This program is distributed in the hope that it will be useful,
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+// but WITHOUT ANY WARRANTY; without even the implied warranty of
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+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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+// GNU General Public License for more details.
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+//
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+// You should have received a copy of the GNU General Public License
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+// along with this program; if not, write to the Free Software
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+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
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+// ======================================================================
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+
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+`timescale 1ns/1ps
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+
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+
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+module tb_cbcmac_des;
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+
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+
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+  // set dumpfile
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+  initial begin
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+    $dumpfile ("tb_cbcmac_des.vcd");
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+    $dumpvars (0, tb_cbcmac_des);
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+  end
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+
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+
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+  reg reset;
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+  reg clk = 0;
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+  reg start;
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+  reg [0:63] key;
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+  reg [0:63] datain;
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+  reg validin;
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+  reg acceptin;
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+  integer index;
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+  integer outdex;
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+  integer errors;
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+  wire [0:63] dataout;
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+  wire validout;
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+  wire acceptout;
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+
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+  reg [0:63] data_input  [0:3];
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+  reg [0:63] key_input = 64'h0123456789abcdef;
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+  reg [0:63] data_output [0:3];
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+
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+  // read in test data files
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+  initial begin
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+    $readmemh("data_input.txt",  data_input);
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+    $readmemh("data_output.txt", data_output);
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+  end
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+
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+
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+  // setup simulation
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+  initial begin
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+    reset = 1;
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+    #1  reset = 0;
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+    #20 reset = 1;
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+  end
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+
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+
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+  // generate clock with 100 mhz
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+  always #5 clk = !clk;
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+
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+
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+  // init the register values
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+  initial
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+    forever @(negedge reset) begin
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+      //disable stimuli;
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+      disable checker;
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+      start   <= 0;
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+      validin <= 0;
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+      key     <= 0;
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+      datain  <= 0;
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+      errors   = 0;
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+    end
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+
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+
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+   // stimuli generator process
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+  initial
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+    forever @(posedge reset) begin
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+      @(posedge clk)
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+        for (index = 0; index < 4; index = index + 1)
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+        begin
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+          @(posedge acceptout)
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+            validin <= 1;
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+            datain  <= data_input[index];
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+            if (index == 0) begin
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+              key   <= key_input;
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+              start <= 1;
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+            end
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+          @(negedge acceptout)
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+            validin <= 0;
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+            start   <= 0;
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+            key     <= 0;
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+        end
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+    end
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+
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+
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+  // checker process
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+  always begin : checker
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+
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+    wait (reset)
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+
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+    acceptin <= 1;
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+
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+    // encryption tests
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+    @(posedge clk)
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+    for(outdex = 0; outdex < 4; outdex = outdex + 1)
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+    begin
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+      @(posedge validout)
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+      // detected an error -> print error message
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+      // increment error counter
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+      if (dataout != data_output[outdex]) begin
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+        $display ("error, output was %h - should have been %h", dataout, data_output[outdex]);
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+        errors = errors + 1;
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+      end
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+    end
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+
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+    // simulation finished -> print messages and if an error was detected
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+    $display   ("#############");
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+    if (errors) begin
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+      $display ("Tests finished, %0d errors detected :(", errors);
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+    end else begin
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+      $display ("Tests finished, no errors detected :)");
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+    end
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+    $display ("#############");
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+
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+    @(posedge clk)
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+      $finish;
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+  end
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+
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+
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+  // dut
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+  cbcmac_des i_cbcmac_des (
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+    .reset_i(reset),
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+    .clk_i(clk),
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+    .start_i(start),
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+    .key_i(key),
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+    .data_i(datain),
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+    .valid_i(validin),
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+    .accept_o(acceptout),
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+    .data_o(dataout),
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+    .valid_o(validout),
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+    .accept_i(acceptin)
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+  );
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+
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+
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+endmodule