T. Meissner 6 years ago
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4dd3f74d15
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      des/sim/verilog/makefile

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des/sim/verilog/makefile View File

@ -47,6 +47,7 @@ wave_pipe : tb_des_pipe.vcd
wave_iter : tb_des_iter.vcd
gtkwave -S tb_des.tcl tb_des_iter.vcd &
.PHONY: clean
clean :
echo "# cleaning simulation files"
rm -f tb_des_*


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