T. Meissner 9 years ago
parent
commit
4dd3f74d15
1 changed files with 1 additions and 0 deletions
  1. +1
    -0
      des/sim/verilog/makefile

+ 1
- 0
des/sim/verilog/makefile View File

@ -47,6 +47,7 @@ wave_pipe : tb_des_pipe.vcd
wave_iter : tb_des_iter.vcd wave_iter : tb_des_iter.vcd
gtkwave -S tb_des.tcl tb_des_iter.vcd & gtkwave -S tb_des.tcl tb_des_iter.vcd &
.PHONY: clean
clean : clean :
echo "# cleaning simulation files" echo "# cleaning simulation files"
rm -f tb_des_* rm -f tb_des_*


Loading…
Cancel
Save