Browse Source

add ITER define; add accept ports to des instance

master
T. Meissner 7 years ago
parent
commit
918483068b
1 changed files with 5 additions and 1 deletions
  1. +5
    -1
      cbcmac_des/rtl/verilog/cbcmac_des.v

+ 5
- 1
cbcmac_des/rtl/verilog/cbcmac_des.v View File

@ -20,6 +20,8 @@
`timescale 1ns/1ps
`define ITER
module cbcmac_des (
input reset_i,
@ -81,8 +83,10 @@ module cbcmac_des (
.key_i(des_key),
.data_i(des_datain),
.valid_i(valid_i),
.accept_o(accept_o),
.data_o(data_o),
.valid_o(valid_o)
.valid_o(valid_o),
.accept_i(accept_i)
);

Loading…
Cancel
Save