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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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172
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1
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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918483068b
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T. Meissner
918483068b
add ITER define; add accept ports to des instance
10 years ago
aes
added prototype of addroundkey() function
11 years ago
cbcdes
moved array type definitions out of functions to head of package, instances now also in package head and are constants
11 years ago
cbcmac_des
add ITER define; add accept ports to des instance
10 years ago
cbctdes
removed internal synced copy of reset_i; set ready to high in reset
11 years ago
des
add support for ITER & PIPE variations of DES verilog implementation
10 years ago
tdes
added removing of tb_tdes binary and *.o files in clean target
11 years ago
.gitignore
added ignore file
11 years ago
LICENSE.textile
added GPLv2 license file
10 years ago