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removed internal synced copy of reset_i; set ready to high in reset

T. Meissner 4 years ago
parent
commit
de08e53153
2 changed files with 9 additions and 15 deletions
  1. 6
    9
      cbctdes/rtl/vhdl/cbctdes.vhd
  2. 3
    6
      cbctdes/rtl/vhdl/tdes.vhd

+ 6
- 9
cbctdes/rtl/vhdl/cbctdes.vhd View File

@@ -62,7 +62,7 @@ architecture rtl of cbctdes is
62 62
       ready_o     : out std_logic
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     );
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   end component tdes;
65
- 
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+
66 66
 
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   signal s_mode       : std_logic;
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   signal s_des_mode   : std_logic;
@@ -83,8 +83,7 @@ architecture rtl of cbctdes is
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   signal s_validout   : std_logic;
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   signal s_ready      : std_logic;
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   signal s_readyout   : std_logic;
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-  signal s_reset      : std_logic;
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- 
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+
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89 88
 begin
90 89
 
@@ -107,7 +106,6 @@ begin
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   inputregister : process(clk_i, reset_i) is
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   begin
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     if(reset_i = '0') then
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-      s_reset    <= '0';
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       s_mode     <= '0';
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       s_start    <= '0';
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       s_key1     <= (others => '0');
@@ -117,7 +115,6 @@ begin
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       s_datain   <= (others => '0');
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       s_datain_d <= (others => '0');
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     elsif(rising_edge(clk_i)) then
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-      s_reset  <= reset_i;
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       if(valid_i = '1' and s_ready = '1') then
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         s_start  <= start_i;
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         s_datain   <= data_i;
@@ -137,23 +134,23 @@ begin
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   outputregister : process(clk_i, reset_i) is
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   begin
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     if(reset_i = '0') then
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-      s_ready   <= '0';
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+      s_ready   <= '1';
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       s_dataout <= (others => '0');
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     elsif(rising_edge(clk_i)) then
143 140
       if(valid_i = '1' and s_ready = '1' and s_readyout = '1') then
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         s_ready <= '0';
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       end if;
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-      if(s_validout = '1' or (reset_i = '1' and s_reset = '0')) then
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+      if(s_validout = '1') then
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         s_ready   <= '1';
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         s_dataout <= s_des_dataout;
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       end if;
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     end if;
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   end process outputregister;
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-      
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+
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   i_tdes : tdes
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     port map (
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-      reset_i => s_reset,
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+      reset_i => reset_i,
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       clk_i   => clk_i,
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       mode_i  => s_des_mode,
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       key1_i  => s_tdes_key1,

+ 3
- 6
cbctdes/rtl/vhdl/tdes.vhd View File

@@ -60,7 +60,6 @@ architecture rtl of tdes is
60 60
 
61 61
 
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   signal s_ready         : std_logic;
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-  signal s_reset         : std_logic;
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   signal s_mode          : std_logic;
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   signal s_des2_mode     : std_logic;
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   signal s_des1_validin  : std_logic := '0';
@@ -90,13 +89,11 @@ begin
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   inputregister : process(clk_i, reset_i) is
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   begin
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     if(reset_i = '0') then
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-      s_reset <= '0';
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       s_mode  <= '0';
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       s_key1  <= (others => '0');
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       s_key2  <= (others => '0');
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       s_key3  <= (others => '0');
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     elsif(rising_edge(clk_i)) then
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-      s_reset  <= reset_i;
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       if(valid_i = '1' and s_ready = '1') then
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         s_mode <= mode_i;
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         s_key1 <= key1_i;
@@ -105,17 +102,17 @@ begin
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       end if;
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     end if;
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   end process inputregister;
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-  
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+
109 106
 
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   outputregister : process(clk_i, reset_i) is
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   begin
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     if(reset_i = '0') then
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-      s_ready   <= '0';
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+      s_ready   <= '1';
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     elsif(rising_edge(clk_i)) then
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       if(valid_i = '1' and s_ready = '1') then
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         s_ready <= '0';
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       end if;
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-      if(s_des3_validout = '1' or (reset_i = '1' and s_reset = '0')) then
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+      if(s_des3_validout = '1') then
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         s_ready   <= '1';
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       end if;
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     end if;