tmeissner
/
cryptocores
Watch 1
Star 0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
Browse Source

removed internal synced copy of reset_i; set ready to high in reset

T. Meissner 4 years ago
parent
4b1f3d11f9
commit
de08e53153
2 changed files with 9 additions and 15 deletions
Split View Show Diff Stats
  1. 6
    9
      cbctdes/rtl/vhdl/cbctdes.vhd
  2. 3
    6
      cbctdes/rtl/vhdl/tdes.vhd

+ 6
- 9
cbctdes/rtl/vhdl/cbctdes.vhd View File 

@@ -62,7 +62,7 @@ architecture rtl of cbctdes is
62 62 
       ready_o     : out std_logic
63 63 
     );
64 64 
   end component tdes;
65 
-
65 
+
66 66
67 67 
   signal s_mode       : std_logic;
68 68 
   signal s_des_mode   : std_logic;
 
@@ -83,8 +83,7 @@ architecture rtl of cbctdes is
83 83 
   signal s_validout   : std_logic;
84 84 
   signal s_ready      : std_logic;
85 85 
   signal s_readyout   : std_logic;
86 
-  signal s_reset      : std_logic;
87 
-
86 
+
88 87
89 88 
 begin
90 89 
 
@@ -107,7 +106,6 @@ begin
107 106 
   inputregister : process(clk_i, reset_i) is
108 107 
   begin
109 108 
     if(reset_i = '0') then
110 
-      s_reset    <= '0';
111 109 
       s_mode     <= '0';
112 110 
       s_start    <= '0';
113 111 
       s_key1     <= (others => '0');
 
@@ -117,7 +115,6 @@ begin
117 115 
       s_datain   <= (others => '0');
118 116 
       s_datain_d <= (others => '0');
119 117 
     elsif(rising_edge(clk_i)) then
120 
-      s_reset  <= reset_i;
121 118 
       if(valid_i = '1' and s_ready = '1') then
122 119 
         s_start  <= start_i;
123 120 
         s_datain   <= data_i;
 
@@ -137,23 +134,23 @@ begin
137 134 
   outputregister : process(clk_i, reset_i) is
138 135 
   begin
139 136 
     if(reset_i = '0') then
140 
-      s_ready   <= '0';
137 
+      s_ready   <= '1';
141 138 
       s_dataout <= (others => '0');
142 139 
     elsif(rising_edge(clk_i)) then
143 140 
       if(valid_i = '1' and s_ready = '1' and s_readyout = '1') then
144 141 
         s_ready <= '0';
145 142 
       end if;
146 
-      if(s_validout = '1' or (reset_i = '1' and s_reset = '0')) then
143 
+      if(s_validout = '1') then
147 144 
         s_ready   <= '1';
148 145 
         s_dataout <= s_des_dataout;
149 146 
       end if;
150 147 
     end if;
151 148 
   end process outputregister;
152 
-
149 
+
153 150
154 151 
   i_tdes : tdes
155 152 
     port map (
156 
-      reset_i => s_reset,
153 
+      reset_i => reset_i,
157 154 
       clk_i   => clk_i,
158 155 
       mode_i  => s_des_mode,
159 156 
       key1_i  => s_tdes_key1,

+ 3
- 6
cbctdes/rtl/vhdl/tdes.vhd View File 

@@ -60,7 +60,6 @@ architecture rtl of tdes is
60 60
61 61
62 62 
   signal s_ready         : std_logic;
63 
-  signal s_reset         : std_logic;
64 63 
   signal s_mode          : std_logic;
65 64 
   signal s_des2_mode     : std_logic;
66 65 
   signal s_des1_validin  : std_logic := '0';
 
@@ -90,13 +89,11 @@ begin
90 89 
   inputregister : process(clk_i, reset_i) is
91 90 
   begin
92 91 
     if(reset_i = '0') then
93 
-      s_reset <= '0';
94 92 
       s_mode  <= '0';
95 93 
       s_key1  <= (others => '0');
96 94 
       s_key2  <= (others => '0');
97 95 
       s_key3  <= (others => '0');
98 96 
     elsif(rising_edge(clk_i)) then
99 
-      s_reset  <= reset_i;
100 97 
       if(valid_i = '1' and s_ready = '1') then
101 98 
         s_mode <= mode_i;
102 99 
         s_key1 <= key1_i;
 
@@ -105,17 +102,17 @@ begin
105 102 
       end if;
106 103 
     end if;
107 104 
   end process inputregister;
108 
-
105 
+
109 106
110 107 
   outputregister : process(clk_i, reset_i) is
111 108 
   begin
112 109 
     if(reset_i = '0') then
113 
-      s_ready   <= '0';
110 
+      s_ready   <= '1';
114 111 
     elsif(rising_edge(clk_i)) then
115 112 
       if(valid_i = '1' and s_ready = '1') then
116 113 
         s_ready <= '0';
117 114 
       end if;
118 
-      if(s_des3_validout = '1' or (reset_i = '1' and s_reset = '0')) then
115 
+      if(s_des3_validout = '1') then
119 116 
         s_ready   <= '1';
120 117 
       end if;
121 118 
     end if;