Browse Source

removed internal synced copy of reset_i; set ready to high in reset

T. Meissner 5 years ago
parent
commit
4b1f3d11f9
2 changed files with 11 additions and 17 deletions
  1. 9
    12
      cbctdes/rtl/verilog/cbctdes.v
  2. 2
    5
      cbctdes/rtl/verilog/tdes.v

+ 9
- 12
cbctdes/rtl/verilog/cbctdes.v View File

@@ -44,9 +44,9 @@ module cbctdes
44 44
   wire        tdes_mode;
45 45
   reg         start;
46 46
   reg  [0:63] key;
47
-  wire [0:63]  tdes_key1;
48
-  wire [0:63]  tdes_key2;
49
-  wire [0:63]  tdes_key3;
47
+  wire [0:63] tdes_key1;
48
+  wire [0:63] tdes_key2;
49
+  wire [0:63] tdes_key3;
50 50
   reg [0:63]  key1;
51 51
   reg [0:63]  key2;
52 52
   reg [0:63]  key3;
@@ -56,7 +56,6 @@ module cbctdes
56 56
   reg  [0:63] tdes_datain;
57 57
   wire        validin;
58 58
   wire [0:63] tdes_dataout;
59
-  reg         reset;
60 59
   reg  [0:63] dataout;
61 60
   wire        tdes_ready;
62 61
 
@@ -97,18 +96,16 @@ module cbctdes
97 96
   // input register
98 97
   always @(posedge clk_i, negedge reset_i) begin
99 98
     if (~reset_i) begin
100
-      reset     <= 0;
101 99
       mode      <= 0;
102 100
       start     <= 0;
103
-      key1 <= 0;
104
-      key2 <= 0;
105
-      key3 <= 0;
101
+      key1      <= 0;
102
+      key2      <= 0;
103
+      key3      <= 0;
106 104
       iv        <= 0;
107 105
       datain    <= 0;
108 106
       datain_d  <= 0;
109 107
     end
110 108
     else begin
111
-      reset <= reset_i;
112 109
       if (valid_i && ready_o) begin
113 110
         start    <= start_i;
114 111
         datain   <= data_i;
@@ -128,14 +125,14 @@ module cbctdes
128 125
     // output register
129 126
   always @(posedge clk_i, negedge reset_i) begin
130 127
     if (~reset_i) begin
131
-      ready_o <= 0;
128
+      ready_o <= 1;
132 129
       dataout <= 0;
133 130
     end
134 131
     else begin
135 132
       if (valid_i && ready_o && tdes_ready) begin
136 133
         ready_o <= 0;
137 134
       end
138
-      else if (valid_o || (reset_i && ~reset)) begin
135
+      else if (valid_o) begin
139 136
         ready_o <= 1;
140 137
         dataout <= tdes_dataout;
141 138
       end
@@ -145,7 +142,7 @@ module cbctdes
145 142
 
146 143
   // des instance
147 144
   tdes i_tdes (
148
-    .reset_i(reset),
145
+    .reset_i(reset_i),
149 146
     .clk_i(clk_i),
150 147
     .mode_i(tdes_mode),
151 148
     .key1_i(tdes_key1),

+ 2
- 5
cbctdes/rtl/verilog/tdes.v View File

@@ -38,7 +38,6 @@ module tdes
38 38
   );
39 39
 
40 40
 
41
-  reg reset;
42 41
   reg mode;
43 42
   reg [0:63] key1;
44 43
   reg [0:63] key2;
@@ -65,14 +64,12 @@ module tdes
65 64
   // input register
66 65
   always @(posedge clk_i, negedge reset_i) begin
67 66
     if (~reset_i) begin
68
-      reset <= 0;
69 67
       mode  <= 0;
70 68
       key1  <= 0;
71 69
       key2  <= 0;
72 70
       key3  <= 0;
73 71
     end
74 72
     else begin
75
-      reset <= reset_i;
76 73
       if (valid_i && ready_o) begin
77 74
         mode <= mode_i;
78 75
         key1 <= key1_i;
@@ -86,13 +83,13 @@ module tdes
86 83
   // output register
87 84
   always @(posedge clk_i, negedge reset_i) begin
88 85
     if (~reset_i) begin
89
-      ready_o <= 0;
86
+      ready_o <= 1;
90 87
     end
91 88
     else begin
92 89
       if (valid_i && ready_o) begin
93 90
         ready_o <= 0;
94 91
       end
95
-      if (valid_o || (reset_i && ~reset)) begin
92
+      if (valid_o) begin
96 93
         ready_o <= 1;
97 94
       end
98 95
     end