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wait for rising edge of s_reset before send stimuli data

T. Meissner 6 years ago
parent
commit
a91d55740a
1 changed files with 7 additions and 6 deletions
  1. 7
    6
      cbctdes/sim/vhdl/tb_cbctdes.vhd

+ 7
- 6
cbctdes/sim/vhdl/tb_cbctdes.vhd View File

@@ -32,7 +32,7 @@ architecture rtl of tb_cbctdes is
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   type t_array is array (natural range <>) of std_logic_vector(0 to 63);
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-  
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+
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   constant c_table_test_plain : t_array(0 to 18) :=
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     (x"01A1D6D039776742", x"5CD54CA83DEF57DA", x"0248D43806F67172",
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      x"51454B582DDF440A", x"42FD443059577FA2", x"059B5E0851CF143A",
@@ -83,7 +83,7 @@ begin
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   s_reset <= '1' after 100 ns;
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   s_clk   <= not(s_clk) after 10 ns;
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- 
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+
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   teststimuliP : process is
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   begin
@@ -95,6 +95,7 @@ begin
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     s_key2    <= (others => '0');
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     s_key3    <= (others => '0');
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     s_datain  <= (others => '0');
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+    wait until s_reset = '1';
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     -- ENCRYPTION TESTS
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     -- cbc known answers test
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     for index in c_table_test_plain'range loop
@@ -148,8 +149,8 @@ begin
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     s_datain  <= (others => '0');
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     wait;
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   end process teststimuliP;
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-  
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-  
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+
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+
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   testcheckerP : process is
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   begin
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     report "# ENCRYPTION TESTS";
@@ -181,10 +182,10 @@ begin
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     key2_i   => s_key2,
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     key3_i   => s_key3,
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     data_i   => s_datain,
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-    valid_i  => s_validin, 
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+    valid_i  => s_validin,
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     data_o   => s_dataout,
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     valid_o  => s_validout,
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-    ready_o  => s_ready              
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+    ready_o  => s_ready
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   );
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