cryptography ip-cores in vhdl / verilog
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cbctdes.vhd 6.0KB

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  1. -- ======================================================================
  2. -- CBC-DES encryption/decryption
  3. -- algorithm according to FIPS 46-3 specification
  4. -- Copyright (C) 2007 Torsten Meissner
  5. -------------------------------------------------------------------------
  6. -- This program is free software; you can redistribute it and/or modify
  7. -- it under the terms of the GNU General Public License as published by
  8. -- the Free Software Foundation; either version 2 of the License, or
  9. -- (at your option) any later version.
  10. -- This program is distributed in the hope that it will be useful,
  11. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. -- GNU General Public License for more details.
  14. -- You should have received a copy of the GNU General Public License
  15. -- along with this program; if not, write to the Free Software
  16. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. -- ======================================================================
  18. library ieee;
  19. use ieee.std_logic_1164.all;
  20. use ieee.numeric_std.all;
  21. use work.des_pkg.all;
  22. entity cbctdes is
  23. port (
  24. reset_i : in std_logic; -- low active async reset
  25. clk_i : in std_logic; -- clock
  26. start_i : in std_logic; -- start cbc
  27. mode_i : in std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
  28. key1_i : in std_logic_vector(0 TO 63); -- key input
  29. key2_i : in std_logic_vector(0 TO 63); -- key input
  30. key3_i : in std_logic_vector(0 TO 63); -- key input
  31. iv_i : in std_logic_vector(0 to 63); -- iv input
  32. data_i : in std_logic_vector(0 TO 63); -- data input
  33. valid_i : in std_logic; -- input key/data valid flag
  34. ready_o : out std_logic; -- ready to encrypt/decrypt
  35. data_o : out std_logic_vector(0 TO 63); -- data output
  36. valid_o : out std_logic -- output data valid flag
  37. );
  38. end entity cbctdes;
  39. architecture rtl of cbctdes is
  40. component tdes is
  41. port (
  42. reset_i : in std_logic; -- async reset
  43. clk_i : in std_logic; -- clock
  44. mode_i : in std_logic; -- tdes-modus: 0 = encrypt, 1 = decrypt
  45. key1_i : in std_logic_vector(0 TO 63); -- key input
  46. key2_i : in std_logic_vector(0 TO 63); -- key input
  47. key3_i : in std_logic_vector(0 TO 63); -- key input
  48. data_i : in std_logic_vector(0 TO 63); -- data input
  49. valid_i : in std_logic; -- input key/data valid flag
  50. data_o : out std_logic_vector(0 TO 63); -- data output
  51. valid_o : out std_logic; -- output data valid flag
  52. ready_o : out std_logic
  53. );
  54. end component tdes;
  55. signal s_mode : std_logic;
  56. signal s_des_mode : std_logic;
  57. signal s_start : std_logic;
  58. signal s_key1 : std_logic_vector(0 to 63);
  59. signal s_key2 : std_logic_vector(0 to 63);
  60. signal s_key3 : std_logic_vector(0 to 63);
  61. signal s_tdes_key1 : std_logic_vector(0 to 63);
  62. signal s_tdes_key2 : std_logic_vector(0 to 63);
  63. signal s_tdes_key3 : std_logic_vector(0 to 63);
  64. signal s_iv : std_logic_vector(0 to 63);
  65. signal s_datain : std_logic_vector(0 to 63);
  66. signal s_datain_d : std_logic_vector(0 to 63);
  67. signal s_des_datain : std_logic_vector(0 to 63);
  68. signal s_validin : std_logic;
  69. signal s_des_dataout : std_logic_vector(0 to 63);
  70. signal s_dataout : std_logic_vector(0 to 63);
  71. signal s_validout : std_logic;
  72. signal s_ready : std_logic;
  73. signal s_readyout : std_logic;
  74. begin
  75. s_des_datain <= iv_i xor data_i when mode_i = '0' and start_i = '1' else
  76. s_dataout xor data_i when s_mode = '0' and start_i = '0' else
  77. data_i;
  78. data_o <= s_iv xor s_des_dataout when s_mode = '1' and s_start = '1' else
  79. s_datain_d xor s_des_dataout when s_mode = '1' and s_start = '0' else
  80. s_des_dataout;
  81. s_tdes_key1 <= key1_i when start_i = '1' else s_key1;
  82. s_tdes_key2 <= key2_i when start_i = '1' else s_key2;
  83. s_tdes_key3 <= key3_i when start_i = '1' else s_key3;
  84. s_des_mode <= mode_i when start_i = '1' else s_mode;
  85. ready_o <= s_ready;
  86. s_validin <= valid_i and s_ready;
  87. valid_o <= s_validout;
  88. inputregister : process(clk_i, reset_i) is
  89. begin
  90. if(reset_i = '0') then
  91. s_mode <= '0';
  92. s_start <= '0';
  93. s_key1 <= (others => '0');
  94. s_key2 <= (others => '0');
  95. s_key3 <= (others => '0');
  96. s_iv <= (others => '0');
  97. s_datain <= (others => '0');
  98. s_datain_d <= (others => '0');
  99. elsif(rising_edge(clk_i)) then
  100. if(valid_i = '1' and s_ready = '1') then
  101. s_start <= start_i;
  102. s_datain <= data_i;
  103. s_datain_d <= s_datain;
  104. end if;
  105. if(valid_i = '1' and s_ready = '1' and start_i = '1') then
  106. s_mode <= mode_i;
  107. s_key1 <= key1_i;
  108. s_key2 <= key2_i;
  109. s_key3 <= key3_i;
  110. s_iv <= iv_i;
  111. end if;
  112. end if;
  113. end process inputregister;
  114. outputregister : process(clk_i, reset_i) is
  115. begin
  116. if(reset_i = '0') then
  117. s_ready <= '1';
  118. s_dataout <= (others => '0');
  119. elsif(rising_edge(clk_i)) then
  120. if(valid_i = '1' and s_ready = '1' and s_readyout = '1') then
  121. s_ready <= '0';
  122. end if;
  123. if(s_validout = '1') then
  124. s_ready <= '1';
  125. s_dataout <= s_des_dataout;
  126. end if;
  127. end if;
  128. end process outputregister;
  129. i_tdes : tdes
  130. port map (
  131. reset_i => reset_i,
  132. clk_i => clk_i,
  133. mode_i => s_des_mode,
  134. key1_i => s_tdes_key1,
  135. key2_i => s_tdes_key2,
  136. key3_i => s_tdes_key3,
  137. data_i => s_des_datain,
  138. valid_i => s_validin,
  139. data_o => s_des_dataout,
  140. valid_o => s_validout,
  141. ready_o => s_readyout
  142. );
  143. end architecture rtl;