cryptography ip-cores in vhdl / verilog
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tdes.vhd 5.0KB

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  1. -- ======================================================================
  2. -- TDES encryption/decryption
  3. -- algorithm according to FIPS 46-3 specification
  4. -- Copyright (C) 2011 Torsten Meissner
  5. -------------------------------------------------------------------------
  6. -- This program is free software; you can redistribute it and/or modify
  7. -- it under the terms of the GNU General Public License as published by
  8. -- the Free Software Foundation; either version 2 of the License, or
  9. -- (at your option) any later version.
  10. -- This program is distributed in the hope that it will be useful,
  11. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. -- GNU General Public License for more details.
  14. -- You should have received a copy of the GNU General Public License
  15. -- along with this program; if not, write to the Free Software
  16. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. -- ======================================================================
  18. library ieee;
  19. use ieee.std_logic_1164.all;
  20. use ieee.numeric_std.all;
  21. use work.des_pkg.all;
  22. entity tdes is
  23. port (
  24. reset_i : in std_logic; -- async reset
  25. clk_i : in std_logic; -- clock
  26. mode_i : in std_logic; -- tdes-modus: 0 = encrypt, 1 = decrypt
  27. key1_i : in std_logic_vector(0 TO 63); -- key input
  28. key2_i : in std_logic_vector(0 TO 63); -- key input
  29. key3_i : in std_logic_vector(0 TO 63); -- key input
  30. data_i : in std_logic_vector(0 TO 63); -- data input
  31. valid_i : in std_logic; -- input key/data valid flag
  32. data_o : out std_logic_vector(0 TO 63); -- data output
  33. valid_o : out std_logic; -- output data valid flag
  34. ready_o : out std_logic
  35. );
  36. end entity tdes;
  37. architecture rtl of tdes is
  38. component des is
  39. port (
  40. reset_i : in std_logic;
  41. clk_i : IN std_logic; -- clock
  42. mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
  43. key_i : IN std_logic_vector(0 TO 63); -- key input
  44. data_i : IN std_logic_vector(0 TO 63); -- data input
  45. valid_i : IN std_logic; -- input key/data valid flag
  46. data_o : OUT std_logic_vector(0 TO 63); -- data output
  47. valid_o : OUT std_logic -- output data valid flag
  48. );
  49. end component des;
  50. signal s_ready : std_logic;
  51. signal s_mode : std_logic;
  52. signal s_des2_mode : std_logic;
  53. signal s_des1_validin : std_logic := '0';
  54. signal s_des1_validout : std_logic;
  55. signal s_des2_validout : std_logic;
  56. signal s_des3_validout : std_logic;
  57. signal s_key1 : std_logic_vector(0 to 63);
  58. signal s_key2 : std_logic_vector(0 to 63);
  59. signal s_key3 : std_logic_vector(0 to 63);
  60. signal s_des1_key : std_logic_vector(0 to 63);
  61. signal s_des3_key : std_logic_vector(0 to 63);
  62. signal s_des1_dataout : std_logic_vector(0 to 63);
  63. signal s_des2_dataout : std_logic_vector(0 to 63);
  64. begin
  65. ready_o <= s_ready;
  66. valid_o <= s_des3_validout;
  67. s_des2_mode <= not(s_mode);
  68. s_des1_validin <= valid_i and s_ready;
  69. s_des1_key <= key1_i when mode_i = '0' else key3_i;
  70. s_des3_key <= s_key3 when s_mode = '0' else s_key1;
  71. inputregister : process(clk_i, reset_i) is
  72. begin
  73. if(reset_i = '0') then
  74. s_mode <= '0';
  75. s_key1 <= (others => '0');
  76. s_key2 <= (others => '0');
  77. s_key3 <= (others => '0');
  78. elsif(rising_edge(clk_i)) then
  79. if(valid_i = '1' and s_ready = '1') then
  80. s_mode <= mode_i;
  81. s_key1 <= key1_i;
  82. s_key2 <= key2_i;
  83. s_key3 <= key3_i;
  84. end if;
  85. end if;
  86. end process inputregister;
  87. outputregister : process(clk_i, reset_i) is
  88. begin
  89. if(reset_i = '0') then
  90. s_ready <= '1';
  91. elsif(rising_edge(clk_i)) then
  92. if(valid_i = '1' and s_ready = '1') then
  93. s_ready <= '0';
  94. end if;
  95. if(s_des3_validout = '1') then
  96. s_ready <= '1';
  97. end if;
  98. end if;
  99. end process outputregister;
  100. i1_des : des
  101. port map (
  102. reset_i => reset_i,
  103. clk_i => clk_i,
  104. mode_i => mode_i,
  105. key_i => s_des1_key,
  106. data_i => data_i,
  107. valid_i => s_des1_validin,
  108. data_o => s_des1_dataout,
  109. valid_o => s_des1_validout
  110. );
  111. i2_des : des
  112. port map (
  113. reset_i => reset_i,
  114. clk_i => clk_i,
  115. mode_i => s_des2_mode,
  116. key_i => s_key2,
  117. data_i => s_des1_dataout,
  118. valid_i => s_des1_validout,
  119. data_o => s_des2_dataout,
  120. valid_o => s_des2_validout
  121. );
  122. i3_des : des
  123. port map (
  124. reset_i => reset_i,
  125. clk_i => clk_i,
  126. mode_i => s_mode,
  127. key_i => s_des3_key,
  128. data_i => s_des2_dataout,
  129. valid_i => s_des2_validout,
  130. data_o => data_o,
  131. valid_o => s_des3_validout
  132. );
  133. end architecture rtl;