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cryptography ip-cores in vhdl / verilog
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cryptocores/des
T. Meissner 3531c69ce1 add support for ITER & PIPE variations of DES verilog implementation 9 years ago
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rtl removed assignments of c & d in r & l process reset state 9 years ago
sim add support for ITER & PIPE variations of DES verilog implementation 9 years ago