|
@@ -103,7 +103,6 @@ begin
|
103
|
103
|
|
104
|
104
|
|
105
|
105
|
process is
|
106
|
|
- variable v_start : std_logic;
|
107
|
106
|
variable v_key : std_logic_vector(0 to 127);
|
108
|
107
|
variable v_nonce : std_logic_vector(0 to C_NONCE_WIDTH-1);
|
109
|
108
|
variable v_datain : std_logic_vector(0 to 127);
|
|
@@ -114,23 +113,19 @@ begin
|
114
|
113
|
wait until s_reset = '1' and rising_edge(s_clk);
|
115
|
114
|
-- ENCRYPTION TESTs
|
116
|
115
|
report "Test CTR-AES encryption";
|
|
116
|
+ s_start <= '1';
|
|
117
|
+ v_nonce := v_random.RandSlv(s_nonce'length);
|
|
118
|
+ v_key := v_random.RandSlv(128);
|
117
|
119
|
for i in 0 to 31 loop
|
118
|
|
- if (i = 0) then
|
119
|
|
- v_start := '1';
|
120
|
|
- v_nonce := v_random.RandSlv(s_nonce'length);
|
121
|
|
- else
|
122
|
|
- v_start := '0';
|
123
|
|
- end if;
|
124
|
|
- v_key := v_random.RandSlv(128);
|
125
|
120
|
v_datain := v_random.RandSlv(128);
|
126
|
|
- s_key <= v_key;
|
127
|
121
|
s_validin <= '1';
|
128
|
|
- s_start <= v_start;
|
|
122
|
+ s_key <= v_key;
|
129
|
123
|
s_nonce <= v_nonce;
|
130
|
124
|
s_datain <= v_datain;
|
131
|
125
|
cryptData(swap(v_datain), swap(v_key), swap(v_nonce & 32x"0"), i = 0, i = 31, v_dataout, v_datain'length/8);
|
132
|
126
|
wait until s_acceptin = '1' and rising_edge(s_clk);
|
133
|
127
|
s_validin <= '0';
|
|
128
|
+ s_start <= '0';
|
134
|
129
|
wait until s_validout = '1' and rising_edge(s_clk);
|
135
|
130
|
s_acceptout <= '1';
|
136
|
131
|
assert s_dataout = swap(v_dataout)
|
|
@@ -141,6 +136,7 @@ begin
|
141
|
136
|
end loop;
|
142
|
137
|
-- Watchdog
|
143
|
138
|
wait for 100 ns;
|
|
139
|
+ report "Simulation finished without errors";
|
144
|
140
|
finish(0);
|
145
|
141
|
end process;
|
146
|
142
|
|