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Fix CTR-init round, set of iv & key in 1st round only.

T. Meissner 1 month ago
parent
commit
b602931174
1 changed files with 6 additions and 10 deletions
  1. 6
    10
      ctraes/sim/vhdl/tb_ctraes.vhd

+ 6
- 10
ctraes/sim/vhdl/tb_ctraes.vhd View File

@@ -103,7 +103,6 @@ begin
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   process is
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-    variable v_start   : std_logic;
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     variable v_key     : std_logic_vector(0 to 127);
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     variable v_nonce   : std_logic_vector(0 to C_NONCE_WIDTH-1);
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     variable v_datain  : std_logic_vector(0 to 127);
@@ -114,23 +113,19 @@ begin
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     wait until s_reset = '1' and rising_edge(s_clk);
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     -- ENCRYPTION TESTs
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     report "Test CTR-AES encryption";
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+    s_start <= '1';
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+    v_nonce := v_random.RandSlv(s_nonce'length);
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+    v_key   := v_random.RandSlv(128);
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     for i in 0 to 31 loop
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-      if (i = 0) then
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-        v_start := '1';
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-        v_nonce := v_random.RandSlv(s_nonce'length);
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-      else
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-        v_start := '0';
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-      end if;
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-      v_key     := v_random.RandSlv(128);
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       v_datain  := v_random.RandSlv(128);
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-      s_key     <= v_key;
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       s_validin <= '1';
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-      s_start   <= v_start;
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+      s_key     <= v_key;
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       s_nonce   <= v_nonce;
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       s_datain  <= v_datain;
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       cryptData(swap(v_datain), swap(v_key), swap(v_nonce & 32x"0"), i = 0, i = 31, v_dataout, v_datain'length/8);
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       wait until s_acceptin = '1' and rising_edge(s_clk);
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       s_validin <= '0';
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+      s_start   <= '0';
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       wait until s_validout = '1' and rising_edge(s_clk);
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       s_acceptout <= '1';
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       assert s_dataout = swap(v_dataout)
@@ -141,6 +136,7 @@ begin
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     end loop;
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     -- Watchdog
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     wait for 100 ns;
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+    report "Simulation finished without errors";
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     finish(0);
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   end process;
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