223 Commits (master)
 

Author SHA1 Message Date
  T. Meissner 918483068b add ITER define; add accept ports to des instance 6 years ago
  T. Meissner 8f575798ea add .PHONY to clean target 6 years ago
  T. Meissner 3531c69ce1 add support for ITER & PIPE variations of DES verilog implementation 6 years ago
  T. Meissner 9454ed15cd removed assignments of c & d in r & l process reset state 6 years ago
  T. Meissner 6dd9c4ad6c removed wrong assignments of r in the c & d process 6 years ago
  T. Meissner cb14f089b9 add acceptin & acceptout ports 6 years ago
  T. Meissner b9efb85f01 add second iterative implementation; selection between the two implementations by #ifdef's 6 years ago
  T. Meissner a65d41bf93 add verilog version of CBCMAC with DES algorithm 6 years ago
  T. Meissner 67df839c95 add implementation & testbench of CBCMAC with DES algorithm 6 years ago
  T. Meissner 393757693e add removing of testbench binary to clean target 6 years ago
  T. Meissner 82ae83f1dc adapted to ITER & PIPE configuration, supports now both settings 6 years ago
  T. Meissner af8fe6023d add accept signals to waveform view 6 years ago
  T. Meissner cfd20a9bbc add removing of object files to clean target 6 years ago
  T. Meissner 5ded08aa7b added GPLv2 license file 6 years ago
  T. Meissner 80443e531d internal mode is now a latched copy of mode_i (ITER) 7 years ago
  T. Meissner 034386b0ce removed forgotten data_o drivers from process 7 years ago
  T. Meissner 1e53c62084 data_o is generated in parallel to sync process now 7 years ago
  T. Meissner 5ebdae8b61 add iterative implementation; config via generic 'design_type' 7 years ago
  T. Meissner 1d061d5dc5 Merge branch 'master' of https://github.com/tmeissner/cryptocores 7 years ago
  T. Meissner 579eab1bf0 removed internal synced copy of reset_i; set ready to high in reset 7 years ago
  T. Meissner 1d858ce952 added removing of tb_tdes binary and *.o files in clean target 7 years ago
  T. Meissner a83081760f added prototype of addroundkey() function 7 years ago
  T. Meissner de08e53153 removed internal synced copy of reset_i; set ready to high in reset 7 years ago
  T. Meissner 4b1f3d11f9 removed internal synced copy of reset_i; set ready to high in reset 7 years ago
  T. Meissner a91d55740a wait for rising edge of s_reset before send stimuli data 7 years ago
  T. Meissner 2a2aa23e21 wait for rising edge of reset before send stimuli data 7 years ago
  T. Meissner ad3f36bbec Merge branch 'master' of https://github.com/tmeissner/cryptocores 7 years ago
  T. Meissner 258e9db1e4 removed internal synced copy of reset; set ready to high in reset 7 years ago
  T. Meissner fa93856e07 removed internal synced copy of reset; set ready to high in reset 7 years ago
  T. Meissner dafb56c966 added wait for disactivated reset before running testcases 7 years ago
  T. Meissner 5c74abc86f added wait for disactivated reset before running testcases 7 years ago
  T. Meissner 62cd1950fe add implementation of mixcolumns function 8 years ago
  T. Meissner a51f0ef35b beauty care 8 years ago
  T. Meissner 8a7e15763a beauty care 8 years ago
  T. Meissner daaca1cc94 beauty care 8 years ago
  T. Meissner 5f15362c4a throw away all ovl stuff 8 years ago
  T. Meissner 0a3a1a9769 throw away all ovl stuff 8 years ago
  T. Meissner 542a5288a4 throw away all ovl stuff 8 years ago
  T. Meissner 6c705cf64b moved array type definitions out of functions to head of package, instances now also in package head and are constants 8 years ago
  T. Meissner a89d5ba3d8 moved array type definitions out of functions to head of package, instances now also in package head and are constants 8 years ago
  T. Meissner 716ce2725b moved array type definitions out of functions to head of package, instances now also in package head and are constants 8 years ago
  T. Meissner 45c9409572 more moving of type & constant definitions to pkg header 8 years ago
  T. Meissner 8d0430ac03 moved array type definitions out of functions to head of package, instances now also in package head and are constants 8 years ago
  T. Meissner e9cd57264b changed option 'T' to 'S' 8 years ago
  T. Meissner d3efde1136 added ignore file 8 years ago
  T. Meissner f8226943a3 changed reset & clk timing according to vhdl testbench 8 years ago
  T. Meissner e62c0d5916 added verilog simulation environment 8 years ago
  T. Meissner 3afaaaf4b2 finished conversion of vhdl design into verilog 8 years ago
  Torsten Meißner f7eb3587cf adapted paths 8 years ago
  T. Meissner f76ae71dd3 beauty care 8 years ago