Browse Source

changed reset & clk timing according to vhdl testbench

T. Meissner 6 years ago
parent
commit
f8226943a3
1 changed files with 3 additions and 3 deletions
  1. 3
    3
      cbctdes/sim/verilog/tb_cbctdes.v

+ 3
- 3
cbctdes/sim/verilog/tb_cbctdes.v View File

@@ -63,11 +63,11 @@ module tb_cbctdes;
63 63
   initial begin
64 64
     reset = 1;
65 65
     #1  reset = 0;
66
-    #20 reset = 1;
66
+    #100 reset = 1;
67 67
   end
68 68
 
69
-    // generate clock with 100 mhz
70
-  always #5 clk = !clk;
69
+    // generate clock with 50 mhz
70
+  always #10 clk = !clk;
71 71
 
72 72
 
73 73
   // init the register values