Merge branch 'master' of https://github.com/tmeissner/cryptocores

tdes/rtl/verilog/tdes.v

@@ -38,7 +38,6 @@ module tdes
   );
 
 
-  reg reset;
   reg mode;
   reg [0:63] key1;
   reg [0:63] key2;
@@ -65,14 +64,12 @@ module tdes
   // input register
   always @(posedge clk_i, negedge reset_i) begin
     if (~reset_i) begin
-      reset <= 0;
       mode  <= 0;
       key1  <= 0;
       key2  <= 0;
       key3  <= 0;
     end
     else begin
-      reset <= reset_i;
       if (valid_i && ready_o) begin
         mode <= mode_i;
         key1 <= key1_i;
@@ -86,13 +83,13 @@ module tdes
   // output register
   always @(posedge clk_i, negedge reset_i) begin
     if (~reset_i) begin
-      ready_o <= 0;
+      ready_o <= 1;
     end
     else begin
       if (valid_i && ready_o) begin
         ready_o <= 0;
       end
-      if (valid_o || (reset_i && ~reset)) begin
+      if (valid_o) begin
         ready_o <= 1;
       end
     end

tdes/rtl/vhdl/tdes.vhd

@@ -64,7 +64,6 @@ architecture rtl of tdes is
 
 
   signal s_ready         : std_logic;
-  signal s_reset         : std_logic;
   signal s_mode          : std_logic;
   signal s_des2_mode     : std_logic;
   signal s_des1_validin  : std_logic := '0';
@@ -94,13 +93,11 @@ begin
   inputregister : process(clk_i, reset_i) is
   begin
     if(reset_i = '0') then
-      s_reset <= '0';
       s_mode  <= '0';
       s_key1  <= (others => '0');
       s_key2  <= (others => '0');
       s_key3  <= (others => '0');
     elsif(rising_edge(clk_i)) then
-      s_reset  <= reset_i;
       if(valid_i = '1' and s_ready = '1') then
         s_mode <= mode_i;
         s_key1 <= key1_i;
@@ -109,17 +106,17 @@ begin
       end if;
     end if;
   end process inputregister;
-  
+
 
   outputregister : process(clk_i, reset_i) is
   begin
     if(reset_i = '0') then
-      s_ready   <= '0';
+      s_ready   <= '1';
     elsif(rising_edge(clk_i)) then
       if(valid_i = '1' and s_ready = '1') then
         s_ready <= '0';
       end if;
-      if(s_des3_validout = '1' or (reset_i = '1' and s_reset = '0')) then
+      if(s_des3_validout = '1') then
         s_ready   <= '1';
       end if;
     end if;

tdes/sim/verilog/tb_tdes.v

@@ -88,6 +88,7 @@ module tb_tdes;
   initial
     forever @(negedge reset) begin
       index = 0;
+      wait (reset);
       while (index < 19) begin
         @(posedge clk)
           if (ready) begin

tdes/sim/vhdl/tb_tdes.vhd

@@ -36,7 +36,7 @@ architecture rtl of tb_tdes is
 
 
   type t_array is array (natural range <>) of std_logic_vector(0 to 63);
-  
+
   constant c_table_test_plain : t_array(0 to 18) :=
     (x"01A1D6D039776742", x"5CD54CA83DEF57DA", x"0248D43806F67172",
      x"51454B582DDF440A", x"42FD443059577FA2", x"059B5E0851CF143A",
@@ -83,7 +83,7 @@ begin
 
   s_reset <= '1' after 100 ns;
   s_clk   <= not(s_clk) after 10 ns;
- 
+
 
   teststimuliP : process is
   begin
@@ -93,6 +93,7 @@ begin
     s_key2    <= (others => '0');
     s_key3    <= (others => '0');
     s_datain  <= (others => '0');
+    wait until s_reset = '1';
     -- ENCRYPTION TESTS
     -- cbc known answers test
     for index in c_table_test_plain'range loop
@@ -136,8 +137,8 @@ begin
     s_datain  <= (others => '0');
     wait;
   end process teststimuliP;
-  
-  
+
+
   testcheckerP : process is
   begin
     report "# ENCRYPTION TESTS";
@@ -167,7 +168,7 @@ begin
     key2_i   => s_key2,
     key3_i   => s_key3,
     data_i   => s_datain,
-    valid_i  => s_validin, 
+    valid_i  => s_validin,
     data_o   => s_dataout,
     valid_o  => s_validout,
     ready_o  => s_ready