Browse Source

removed internal synced copy of reset; set ready to high in reset

T. Meissner 5 years ago
parent
commit
258e9db1e4
1 changed files with 3 additions and 6 deletions
  1. 3
    6
      tdes/rtl/vhdl/tdes.vhd

+ 3
- 6
tdes/rtl/vhdl/tdes.vhd View File

@@ -64,7 +64,6 @@ architecture rtl of tdes is
64 64
 
65 65
 
66 66
   signal s_ready         : std_logic;
67
-  signal s_reset         : std_logic;
68 67
   signal s_mode          : std_logic;
69 68
   signal s_des2_mode     : std_logic;
70 69
   signal s_des1_validin  : std_logic := '0';
@@ -94,13 +93,11 @@ begin
94 93
   inputregister : process(clk_i, reset_i) is
95 94
   begin
96 95
     if(reset_i = '0') then
97
-      s_reset <= '0';
98 96
       s_mode  <= '0';
99 97
       s_key1  <= (others => '0');
100 98
       s_key2  <= (others => '0');
101 99
       s_key3  <= (others => '0');
102 100
     elsif(rising_edge(clk_i)) then
103
-      s_reset  <= reset_i;
104 101
       if(valid_i = '1' and s_ready = '1') then
105 102
         s_mode <= mode_i;
106 103
         s_key1 <= key1_i;
@@ -109,17 +106,17 @@ begin
109 106
       end if;
110 107
     end if;
111 108
   end process inputregister;
112
-  
109
+
113 110
 
114 111
   outputregister : process(clk_i, reset_i) is
115 112
   begin
116 113
     if(reset_i = '0') then
117
-      s_ready   <= '0';
114
+      s_ready   <= '1';
118 115
     elsif(rising_edge(clk_i)) then
119 116
       if(valid_i = '1' and s_ready = '1') then
120 117
         s_ready <= '0';
121 118
       end if;
122
-      if(s_des3_validout = '1' or (reset_i = '1' and s_reset = '0')) then
119
+      if(s_des3_validout = '1') then
123 120
         s_ready   <= '1';
124 121
       end if;
125 122
     end if;