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added wait for disactivated reset before running testcases

master
T. Meissner 10 years ago
parent
commit
5c74abc86f
1 changed files with 1 additions and 0 deletions
  1. +1
    -0
      tdes/sim/verilog/tb_tdes.v

+ 1
- 0
tdes/sim/verilog/tb_tdes.v View File

@ -88,6 +88,7 @@ module tb_tdes;
initial
forever @(negedge reset) begin
index = 0;
wait (reset);
while (index < 19) begin
@(posedge clk)
if (ready) begin


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