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  • 5640e78 (HEAD -> master) Update CBCDES unit and tests by tmeissner 2020-07-27 12:22:41 +0200
  • a2c5309 Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring by tmeissner 2020-07-26 22:17:52 +0200
  • 1850e5c Add Makefiles for VHDL synthesis of DES & TDES by tmeissner 2020-07-24 23:00:49 +0200
  • 2e48c18 Some Makefile refactoring by tmeissner 2020-07-17 22:39:49 +0200
  • cc268c2 Fix osvvm path by tmeissner 2020-07-17 16:43:46 +0200
  • c5a7007 Implement key schedule for AES decryption, unoptimized by tmeissner 2020-07-17 16:43:29 +0200
  • 1dc2fd2 Use co-sim for descryption tests also by tmeissner 2020-07-15 16:52:52 +0200
  • 51d7b48 Make PSL compatible with simulation & synthesis by tmeissner 2020-07-15 16:17:42 +0200
  • 0a7ed33 Use co-sim with openSSL to check AES enc VHDL implementation by tmeissner 2020-07-15 15:19:12 +0200
  • d16c247 Add OSVVM as submodule by tmeissner 2020-07-15 14:36:41 +0200
  • 491b4df Move PSL stuff in generate block; add formal PSL code by tmeissner 2020-07-13 16:10:51 +0200
  • 303bda2 Add CTR-AES VHDL design by tmeissner 2020-07-11 15:48:16 +0200
  • dce8396 Refactoring; remove unused functions by tmeissner 2020-07-11 15:46:37 +0200
  • 50aaca8 Fix PSL cover directives by tmeissner 2020-07-11 15:45:37 +0200
  • b7b9f36 Add CBCMAC-AES VHDL design by tmeissner 2020-07-09 10:45:58 +0200
  • 28b2cd3 Implement key schedule for encryption, finally by tmeissner 2020-07-08 19:50:54 +0200
  • be5b8af (wip) Add subword() function by Torsten Meissner 2019-04-02 17:19:57 +0200
  • b59791e Move VHDL library files in work directory by Torsten Meissner 2019-03-12 14:19:32 +0100
  • 77f8753 FSM optimizations; PSL enhancements by Torsten Meissner 2019-03-12 13:59:45 +0100
  • c400d2e Add PSL checkers, refactoring by Torsten Meissner 2019-03-01 11:41:42 +0100
  • 735c411 First working version of AES enc & dec by tmeissner 2019-02-28 22:55:01 +0100
  • d8ca919 Fixed many incorrect implemented functions by tmeissner 2019-02-23 16:22:50 +0100
  • 42a5eb9 Minor refactoring & bugfixing by Torsten Meissner 2019-02-20 16:29:46 +0100
  • 27e06df Fix gmul() & (inv)mixcolums() functions by tmeissner 2019-02-19 23:49:48 +0100
  • 517237c Created Readme.md file by T. Meissner 2016-09-04 12:39:46 +0200
  • 2f91130 Add remaining AES functions by tmeissner 2015-11-18 20:52:25 +0100
  • 46f1b92 merge last changes from amc mini repo by tmeissner 2015-05-29 19:14:16 +0200
  • 8a9b309 integrate s1-s8() into one s() function with additional parameter s_table; convert lower to upper case by tmeissner 2015-04-03 19:17:01 +0200
  • 313a08b add verilog simulation environment for cbcmac-des by tmeissner 2015-04-03 16:57:17 +0200
  • 4dd3f74 Merge branch 'master' of https://github.com/tmeissner/cryptocores by tmeissner 2015-04-03 15:18:29 +0200
  • 9184830 add ITER define; add accept ports to des instance by tmeissner 2015-04-03 15:18:04 +0200
  • 8f57579 add .PHONY to clean target by T. Meissner 2015-03-26 12:14:34 +0100
  • 3531c69 add support for ITER & PIPE variations of DES verilog implementation by tmeissner 2015-03-25 22:56:49 +0100
  • 9454ed1 removed assignments of c & d in r & l process reset state by tmeissner 2015-03-25 00:52:49 +0100
  • 6dd9c4a removed wrong assignments of r in the c & d process by tmeissner 2015-03-25 00:51:03 +0100
  • cb14f08 add acceptin & acceptout ports by tmeissner 2015-03-25 00:47:57 +0100
  • b9efb85 add second iterative implementation; selection between the two implementations by #ifdef's by tmeissner 2015-03-25 00:47:00 +0100
  • a65d41b add verilog version of CBCMAC with DES algorithm by tmeissner 2015-03-22 23:39:09 +0100
  • 67df839 add implementation & testbench of CBCMAC with DES algorithm by tmeissner 2015-03-22 23:05:56 +0100
  • 3937576 add removing of testbench binary to clean target by tmeissner 2015-03-22 13:49:08 +0100
  • 82ae83f adapted to ITER & PIPE configuration, supports now both settings by tmeissner 2015-03-22 12:50:08 +0100
  • af8fe60 add accept signals to waveform view by tmeissner 2015-03-22 12:47:27 +0100
  • cfd20a9 add removing of object files to clean target by tmeissner 2015-03-22 12:46:46 +0100
  • 5ded08a added GPLv2 license file by tmeissner 2015-03-09 21:50:52 +0100
  • 80443e5 internal mode is now a latched copy of mode_i (ITER) by tmeissner 2014-12-14 02:44:28 +0100
  • 034386b removed forgotten data_o drivers from process by tmeissner 2014-12-14 02:07:47 +0100
  • 1e53c62 data_o is generated in parallel to sync process now by tmeissner 2014-12-14 02:04:58 +0100
  • 5ebdae8 add iterative implementation; config via generic 'design_type' by tmeissner 2014-12-14 01:42:56 +0100
  • 1d061d5 Merge branch 'master' of https://github.com/tmeissner/cryptocores by tmeissner 2014-07-08 20:43:37 +0200
  • 579eab1 removed internal synced copy of reset_i; set ready to high in reset by tmeissner 2014-07-08 20:43:18 +0200
  • 1d858ce added removing of tb_tdes binary and *.o files in clean target by tmeissner 2014-07-08 20:42:24 +0200
  • a830817 added prototype of addroundkey() function by tmeissner 2014-07-08 01:34:54 +0200
  • de08e53 removed internal synced copy of reset_i; set ready to high in reset by tmeissner 2014-07-08 01:34:00 +0200
  • 4b1f3d1 removed internal synced copy of reset_i; set ready to high in reset by tmeissner 2014-07-08 01:33:19 +0200
  • a91d557 wait for rising edge of s_reset before send stimuli data by tmeissner 2014-07-08 01:31:55 +0200
  • 2a2aa23 wait for rising edge of reset before send stimuli data by tmeissner 2014-07-08 01:30:56 +0200
  • ad3f36b Merge branch 'master' of https://github.com/tmeissner/cryptocores by tmeissner 2014-07-08 01:12:44 +0200
  • 258e9db removed internal synced copy of reset; set ready to high in reset by tmeissner 2014-07-07 12:30:15 +0200
  • fa93856 removed internal synced copy of reset; set ready to high in reset by tmeissner 2014-07-07 12:29:59 +0200
  • dafb56c added wait for disactivated reset before running testcases by tmeissner 2014-07-07 12:29:08 +0200
  • 5c74abc added wait for disactivated reset before running testcases by tmeissner 2014-07-07 12:28:11 +0200
  • 62cd195 add implementation of mixcolumns function by tmeissner 2013-12-29 17:12:59 +0100
  • a51f0ef beauty care by tmeissner 2013-12-29 16:14:59 +0100
  • 8a7e157 beauty care by tmeissner 2013-12-29 16:14:46 +0100
  • daaca1c beauty care by tmeissner 2013-12-29 16:14:04 +0100
  • 5f15362 throw away all ovl stuff by tmeissner 2013-12-29 16:10:54 +0100
  • 0a3a1a9 throw away all ovl stuff by tmeissner 2013-12-29 16:05:41 +0100
  • 542a528 throw away all ovl stuff by tmeissner 2013-12-29 16:04:43 +0100
  • 6c705cf moved array type definitions out of functions to head of package, instances now also in package head and are constants by tmeissner 2013-12-28 19:07:15 +0100
  • a89d5ba moved array type definitions out of functions to head of package, instances now also in package head and are constants by tmeissner 2013-12-28 19:07:06 +0100
  • 716ce27 moved array type definitions out of functions to head of package, instances now also in package head and are constants by tmeissner 2013-12-28 19:06:58 +0100
  • 45c9409 more moving of type & constant definitions to pkg header by tmeissner 2013-12-28 19:04:51 +0100
  • 8d0430a moved array type definitions out of functions to head of package, instances now also in package head and are constants by tmeissner 2013-12-28 18:21:25 +0100
  • e9cd572 changed option 'T' to 'S' by tmeissner 2013-12-28 18:17:40 +0100
  • d3efde1 added ignore file by tmeissner 2013-12-28 18:16:52 +0100
  • f822694 changed reset & clk timing according to vhdl testbench by tmeissner 2013-12-28 01:16:23 +0100
  • e62c0d5 added verilog simulation environment by tmeissner 2013-12-28 00:45:08 +0100
  • 3afaaaf finished conversion of vhdl design into verilog by tmeissner 2013-12-28 00:44:20 +0100
  • f7eb358 adapted paths by Torsten Meißner 2013-12-28 00:02:00 +0100
  • f76ae71 beauty care by tmeissner 2013-03-28 20:25:53 +0100
  • b6fdf6b initial commit of cbcdes verilog verification sources by tmeissner 2013-03-28 20:24:48 +0100
  • 7105d21 iunitial commit os cbctdes verilog sources by tmeissner 2013-03-28 20:20:13 +0100
  • 67fdd7e moved in seperate directory 'vhdl' by Torsten Meissner 2013-03-26 20:43:45 +0100
  • 20f0bac moved in seperate directory 'vhdl' by Torsten Meissner 2013-03-26 20:42:15 +0100
  • 0c70ec5 initial commit of verilog simulation environment for verilog cbcdes core by tmeissner 2013-03-25 00:18:41 +0100
  • 4489748 initial commit os CBCDES verilog design file by tmeissner 2013-03-25 00:17:36 +0100
  • 51745c4 adapt to new directory structure by tmeissner 2013-03-25 00:15:35 +0100
  • 8c33d73 moved in seperate directory 'vhdl' by tmeissner 2013-03-25 00:13:02 +0100
  • cb76c16 moved in seperate directory 'vhdl' by tmeissner 2013-03-25 00:12:50 +0100
  • e8aff41 bugfixes to make tdes.v core working correctly by tmeissner 2013-03-24 23:47:30 +0100
  • 5fff1d8 initial commit of verilog simulation environment for tdes core by tmeissner 2013-03-24 23:46:21 +0100
  • 553e105 Merge branch 'master' of https://github.com/tmeissner/cryptocores by tmeissner 2013-03-24 17:39:09 +0100
  • e2225fb initial commit os TDES verilog design file by Torsten Meissner 2013-03-24 16:37:16 +0100
  • 45403f1 import of des verilog design files by Torsten Meissner 2013-03-24 16:07:15 +0100
  • dd979b5 adapt makefile to new directory structure; new variable SRC_FILES for vhdl sources by Torsten Meissner 2013-03-24 16:05:44 +0100
  • 715b8b1 beauty care by Torsten Meissner 2013-03-24 16:05:13 +0100
  • 30a7af4 moved into seperate vhdl folder by Torsten Meissner 2013-03-24 16:00:37 +0100
  • 5e42292 moved into seperate vhdl folder by Torsten Meissner 2013-03-24 16:00:21 +0100
  • d779f5a moved into seperate vhdl folder by Torsten Meissner 2013-03-24 15:59:10 +0100
  • 7822728 moved into seperate vhdl folder by Torsten Meissner 2013-03-24 15:58:51 +0100