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Update CBCDES unit and tests

* Use des from des dir instead of local copies
* Adapt testbench to des interface
* Add Makefile for VHDL-synthesis
T. Meissner 3 months ago
parent
commit
5640e7884b

+ 35
- 60
cbcdes/rtl/vhdl/cbcdes.vhd View File

@@ -37,13 +37,14 @@ entity cbcdes is
37 37
     clk_i       : in  std_logic;                  -- clock
38 38
     start_i     : in  std_logic;                  -- start cbc
39 39
     mode_i      : in  std_logic;                  -- des-modus: 0 = encrypt, 1 = decrypt
40
-    key_i       : in  std_logic_vector(0 TO 63);  -- key input
40
+    key_i       : in  std_logic_vector(0 to 63);  -- key input
41 41
     iv_i        : in  std_logic_vector(0 to 63);  -- iv input
42
-    data_i      : in  std_logic_vector(0 TO 63);  -- data input
42
+    data_i      : in  std_logic_vector(0 to 63);  -- data input
43 43
     valid_i     : in  std_logic;                  -- input key/data valid flag
44
-    ready_o     : out std_logic;                  -- ready to encrypt/decrypt
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-    data_o      : out std_logic_vector(0 TO 63);  -- data output
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-    valid_o     : out std_logic                   -- output data valid flag
44
+    accept_o    : out std_logic;                  -- ready to encrypt/decrypt
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+    data_o      : out std_logic_vector(0 to 63);  -- data output
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+    valid_o     : out std_logic;                   -- output data valid flag
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+    accept_i    : in  std_logic
47 48
   );
48 49
 end entity cbcdes;
49 50
 
@@ -51,20 +52,6 @@ end entity cbcdes;
51 52
 architecture rtl of cbcdes is
52 53
 
53 54
 
54
-  component des is
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-    port (
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-      reset_i     : in  std_logic;
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-      clk_i       : IN  std_logic;                  -- clock
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-      mode_i      : IN  std_logic;                  -- des-modus: 0 = encrypt, 1 = decrypt
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-      key_i       : IN  std_logic_vector(0 TO 63);  -- key input
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-      data_i      : IN  std_logic_vector(0 TO 63);  -- data input
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-      valid_i     : IN  std_logic;                  -- input key/data valid flag
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-      data_o      : OUT std_logic_vector(0 TO 63);  -- data output
63
-      valid_o     : OUT std_logic                   -- output data valid flag
64
-    );
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-  end component des;
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- 
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-
68 55
   signal s_mode       : std_logic;
69 56
   signal s_des_mode   : std_logic;
70 57
   signal s_start      : std_logic;
@@ -74,83 +61,71 @@ architecture rtl of cbcdes is
74 61
   signal s_datain     : std_logic_vector(0 to 63);
75 62
   signal s_datain_d   : std_logic_vector(0 to 63);
76 63
   signal s_des_datain : std_logic_vector(0 to 63);
77
-  signal s_validin    : std_logic;
78 64
   signal s_des_dataout : std_logic_vector(0 to 63);
79 65
   signal s_dataout    : std_logic_vector(0 to 63);
80
-  signal s_validout   : std_logic;
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-  signal s_ready      : std_logic;
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-  signal s_reset      : std_logic;
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- 
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+
84 67
 
85 68
 begin
86 69
 
87 70
 
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-  s_des_datain <= iv_i xor data_i      when mode_i = '0' and start_i = '1' else
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+  s_des_datain <= iv_i      xor data_i when mode_i = '0' and start_i = '1' else
89 72
                   s_dataout xor data_i when s_mode = '0' and start_i = '0' else
90 73
                   data_i;
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-  data_o       <= s_iv xor s_des_dataout     when s_mode = '1' and s_start = '1' else
74
+  data_o       <= s_iv       xor s_des_dataout when s_mode = '1' and s_start = '1' else
92 75
                   s_datain_d xor s_des_dataout when s_mode = '1' and s_start = '0' else
93 76
                   s_des_dataout;
94 77
   s_des_key    <= key_i  when start_i = '1' else s_key;
95 78
   s_des_mode   <= mode_i when start_i = '1' else s_mode;
96 79
 
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-  ready_o     <= s_ready;
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-  s_validin   <= valid_i and s_ready;
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-  valid_o     <= s_validout;
100 80
 
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-  inputregister : process(clk_i, reset_i) is
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+  inputregister : process (clk_i, reset_i) is
102 82
   begin
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-    if(reset_i = '0') then
104
-      s_reset    <= '0';
83
+    if (reset_i = '0') then
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       s_mode     <= '0';
106 85
       s_start    <= '0';
107 86
       s_key      <= (others => '0');
108 87
       s_iv       <= (others => '0');
109 88
       s_datain   <= (others => '0');
110 89
       s_datain_d <= (others => '0');
111
-    elsif(rising_edge(clk_i)) then
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-      s_reset  <= reset_i;
113
-      if(valid_i = '1' and s_ready = '1') then
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-        s_start  <= start_i;
90
+    elsif (rising_edge(clk_i)) then
91
+      if (valid_i = '1' and accept_o = '1') then
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+        s_start    <= start_i;
115 93
         s_datain   <= data_i;
116 94
         s_datain_d <= s_datain;
117
-      end if;
118
-      if(valid_i = '1' and s_ready = '1' and start_i = '1') then
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-        s_mode   <= mode_i;
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-        s_key    <= key_i;
121
-        s_iv     <= iv_i;
95
+        if (start_i = '1') then
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+          s_mode <= mode_i;
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+          s_key  <= key_i;
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+          s_iv   <= iv_i;
99
+        end if;
122 100
       end if;
123 101
     end if;
124 102
   end process inputregister;
125 103
 
126 104
 
127
-  outputregister : process(clk_i, reset_i) is
105
+  outputregister : process (clk_i, reset_i) is
128 106
   begin
129
-    if(reset_i = '0') then
130
-      s_ready   <= '0';
107
+    if (reset_i = '0') then
131 108
       s_dataout <= (others => '0');
132
-    elsif(rising_edge(clk_i)) then
133
-      if(valid_i = '1' and s_ready = '1') then
134
-        s_ready <= '0';
135
-      end if;
136
-      if(s_validout = '1' or (reset_i = '1' and s_reset = '0')) then
137
-        s_ready   <= '1';
109
+    elsif (rising_edge(clk_i)) then
110
+      if (valid_o = '1' and accept_i = '1') then
138 111
         s_dataout <= s_des_dataout;
139 112
       end if;
140 113
     end if;
141 114
   end process outputregister;
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-      
143 115
 
144
-  i_des : des
116
+
117
+  i_des : entity work.des
145 118
     port map (
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-      reset_i => s_reset,
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-      clk_i   => clk_i,
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-      mode_i  => s_des_mode,
149
-      key_i   => s_des_key,
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-      data_i  => s_des_datain,
151
-      valid_i => s_validin,
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-      data_o  => s_des_dataout,
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-      valid_o => s_validout
119
+      reset_i  => reset_i,
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+      clk_i    => clk_i,
121
+      mode_i   => s_des_mode,
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+      key_i    => s_des_key,
123
+      data_i   => s_des_datain,
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+      valid_i  => valid_i,
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+      accept_o => accept_o,
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+      data_o   => s_des_dataout,
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+      valid_o  => valid_o,
128
+      accept_i => accept_i
154 129
     );
155 130
 
156 131
 

+ 0
- 320
cbcdes/rtl/vhdl/des.vhd View File

@@ -1,340 +0,0 @@
1
--------------------------------------------------------------------------
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-
3
-
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-
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-
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-
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-
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-LIBRARY ieee;
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-USE ieee.std_logic_1164.all;
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-USE ieee.numeric_std.ALL;
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-USE work.des_pkg.ALL;
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-
13
-
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-ENTITY des IS
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-  PORT (
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-    reset_i     : in  std_logic;                  -- async reset
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-    clk_i       : IN  std_logic;                  -- clock
18
-    mode_i      : IN  std_logic;                  -- des-modus: 0 = encrypt, 1 = decrypt
19
-    key_i       : IN  std_logic_vector(0 TO 63);  -- key input
20
-    data_i      : IN  std_logic_vector(0 TO 63);  -- data input
21
-    valid_i     : IN  std_logic;                  -- input key/data valid flag
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-    data_o      : OUT std_logic_vector(0 TO 63);  -- data output
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-    valid_o     : OUT std_logic                   -- output data valid flag
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-  );
25
-END ENTITY des;
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-
27
-
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-ARCHITECTURE rtl OF des IS
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-
30
-BEGIN
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-
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-  crypt : PROCESS ( clk_i ) IS
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-    -- variables for key calculation
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-    VARIABLE c0  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE c1  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE c2  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE c3  : std_logic_vector(0 TO 27) := (others => '0');
38
-    VARIABLE c4  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE c5  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE c6  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE c7  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE c8  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE c9  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE c10 : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE c11 : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE c12 : std_logic_vector(0 TO 27) := (others => '0');
47
-    VARIABLE c13 : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE c14 : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE c15 : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE c16 : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE d0  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE d1  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE d2  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE d3  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE d4  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE d5  : std_logic_vector(0 TO 27) := (others => '0');
57
-    VARIABLE d6  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE d7  : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE d8  : std_logic_vector(0 TO 27) := (others => '0');
60
-    VARIABLE d9  : std_logic_vector(0 TO 27) := (others => '0');
61
-    VARIABLE d10 : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE d11 : std_logic_vector(0 TO 27) := (others => '0');
63
-    VARIABLE d12 : std_logic_vector(0 TO 27) := (others => '0');
64
-    VARIABLE d13 : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE d14 : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE d15 : std_logic_vector(0 TO 27) := (others => '0');
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-    VARIABLE d16 : std_logic_vector(0 TO 27) := (others => '0');
68
-    -- key variables
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-    VARIABLE key1  : std_logic_vector(0 TO 47) := (others => '0');
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-    VARIABLE key2  : std_logic_vector(0 TO 47) := (others => '0');
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-    VARIABLE key3  : std_logic_vector(0 TO 47) := (others => '0');
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-    VARIABLE key4  : std_logic_vector(0 TO 47) := (others => '0');
73
-    VARIABLE key5  : std_logic_vector(0 TO 47) := (others => '0');
74
-    VARIABLE key6  : std_logic_vector(0 TO 47) := (others => '0');
75
-    VARIABLE key7  : std_logic_vector(0 TO 47) := (others => '0');
76
-    VARIABLE key8  : std_logic_vector(0 TO 47) := (others => '0');
77
-    VARIABLE key9  : std_logic_vector(0 TO 47) := (others => '0');
78
-    VARIABLE key10 : std_logic_vector(0 TO 47) := (others => '0');
79
-    VARIABLE key11 : std_logic_vector(0 TO 47) := (others => '0');
80
-    VARIABLE key12 : std_logic_vector(0 TO 47) := (others => '0');
81
-    VARIABLE key13 : std_logic_vector(0 TO 47) := (others => '0');
82
-    VARIABLE key14 : std_logic_vector(0 TO 47) := (others => '0');
83
-    VARIABLE key15 : std_logic_vector(0 TO 47) := (others => '0');
84
-    VARIABLE key16 : std_logic_vector(0 TO 47) := (others => '0');
85
-    -- variables for left & right data blocks
86
-    VARIABLE l0  : std_logic_vector( 0 TO 31) := (others => '0');
87
-    VARIABLE l1  : std_logic_vector( 0 TO 31) := (others => '0');
88
-    VARIABLE l2  : std_logic_vector( 0 TO 31) := (others => '0');
89
-    VARIABLE l3  : std_logic_vector( 0 TO 31) := (others => '0');
90
-    VARIABLE l4  : std_logic_vector( 0 TO 31) := (others => '0');
91
-    VARIABLE l5  : std_logic_vector( 0 TO 31) := (others => '0');
92
-    VARIABLE l6  : std_logic_vector( 0 TO 31) := (others => '0');
93
-    VARIABLE l7  : std_logic_vector( 0 TO 31) := (others => '0');
94
-    VARIABLE l8  : std_logic_vector( 0 TO 31) := (others => '0');
95
-    VARIABLE l9  : std_logic_vector( 0 TO 31) := (others => '0');
96
-    VARIABLE l10 : std_logic_vector( 0 TO 31) := (others => '0');
97
-    VARIABLE l11 : std_logic_vector( 0 TO 31) := (others => '0');
98
-    VARIABLE l12 : std_logic_vector( 0 TO 31) := (others => '0');
99
-    VARIABLE l13 : std_logic_vector( 0 TO 31) := (others => '0');
100
-    VARIABLE l14 : std_logic_vector( 0 TO 31) := (others => '0');
101
-    VARIABLE l15 : std_logic_vector( 0 TO 31) := (others => '0');
102
-    VARIABLE l16 : std_logic_vector( 0 TO 31) := (others => '0');
103
-    VARIABLE r0  : std_logic_vector( 0 TO 31) := (others => '0');
104
-    VARIABLE r1  : std_logic_vector( 0 TO 31) := (others => '0');
105
-    VARIABLE r2  : std_logic_vector( 0 TO 31) := (others => '0');
106
-    VARIABLE r3  : std_logic_vector( 0 TO 31) := (others => '0');
107
-    VARIABLE r4  : std_logic_vector( 0 TO 31) := (others => '0');
108
-    VARIABLE r5  : std_logic_vector( 0 TO 31) := (others => '0');
109
-    VARIABLE r6  : std_logic_vector( 0 TO 31) := (others => '0');
110
-    VARIABLE r7  : std_logic_vector( 0 TO 31) := (others => '0');
111
-    VARIABLE r8  : std_logic_vector( 0 TO 31) := (others => '0');
112
-    VARIABLE r9  : std_logic_vector( 0 TO 31) := (others => '0');
113
-    VARIABLE r10 : std_logic_vector( 0 TO 31) := (others => '0');
114
-    VARIABLE r11 : std_logic_vector( 0 TO 31) := (others => '0');
115
-    VARIABLE r12 : std_logic_vector( 0 TO 31) := (others => '0');
116
-    VARIABLE r13 : std_logic_vector( 0 TO 31) := (others => '0');
117
-    VARIABLE r14 : std_logic_vector( 0 TO 31) := (others => '0');
118
-    VARIABLE r15 : std_logic_vector( 0 TO 31) := (others => '0');
119
-    VARIABLE r16 : std_logic_vector( 0 TO 31) := (others => '0');
120
-    -- variables for mode & valid shift registers
121
-    VARIABLE mode  : std_logic_vector(0 TO 16) := (others => '0');
122
-    VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0');
123
-  BEGIN
124
-    if(reset_i = '0') then
125
-      data_o  <= (others => '0');
126
-      valid_o <= '0';
127
-    elsif rising_edge( clk_i ) THEN
128
-      -- shift registers
129
-      valid(1 TO 17) := valid(0 TO 16);
130
-      valid(0) := valid_i;
131
-      mode(1 TO 16) := mode(0 TO 15);
132
-      mode(0)  := mode_i;
133
-      -- output stage
134
-      valid_o <= valid(17);
135
-      data_o  <= ipn( ( r16 & l16 ) );
136
-      -- 16. stage
137
-      IF mode(16) = '0' THEN
138
-        c16 := c15(1 TO 27) & c15(0);
139
-        d16 := d15(1 TO 27) & d15(0);
140
-      ELSE
141
-        c16 := c15(27) & c15(0 TO 26);
142
-        d16 := d15(27) & d15(0 TO 26);
143
-      END IF;
144
-      key16 := pc2( ( c16 & d16 ) );
145
-      l16 := r15;
146
-      r16 := l15 xor ( f( r15, key16 ) );
147
-      -- 15. stage
148
-      IF mode(15) = '0' THEN
149
-        c15 := c14(2 TO 27) & c14(0 TO 1);
150
-        d15 := d14(2 TO 27) & d14(0 TO 1);
151
-      ELSE
152
-        c15 := c14(26 TO 27) & c14(0 TO 25);
153
-        d15 := d14(26 TO 27) & d14(0 TO 25);
154
-      END IF;
155
-      key15 := pc2( ( c15 & d15 ) );
156
-      l15 := r14;
157
-      r15 := l14 xor ( f( r14, key15 ) );
158
-      -- 14. stage
159
-      IF mode(14) = '0' THEN
160
-        c14 := c13(2 TO 27) & c13(0 TO 1);
161
-        d14 := d13(2 TO 27) & d13(0 TO 1);
162
-      ELSE
163
-        c14 := c13(26 TO 27) & c13(0 TO 25);
164
-        d14 := d13(26 TO 27) & d13(0 TO 25);
165
-      END IF;
166
-      key14 := pc2( ( c14 & d14 ) );
167
-      l14 := r13;
168
-      r14 := l13 xor ( f( r13, key14 ) );
169
-      -- 13. stage
170
-      IF mode(13) = '0' THEN
171
-        c13 := c12(2 TO 27) & c12(0 TO 1);
172
-        d13 := d12(2 TO 27) & d12(0 TO 1);
173
-      ELSE
174
-        c13 := c12(26 TO 27) & c12(0 TO 25);
175
-        d13 := d12(26 TO 27) & d12(0 TO 25);
176
-      END IF;
177
-      key13 := pc2( ( c13 & d13 ) );
178
-      l13 := r12;
179
-      r13 := l12 xor ( f( r12, key13 ) );
180
-      -- 12. stage
181
-      IF mode(12) = '0' THEN
182
-        c12 := c11(2 TO 27) & c11(0 TO 1);
183
-        d12 := d11(2 TO 27) & d11(0 TO 1);
184
-      ELSE
185
-        c12 := c11(26 TO 27) & c11(0 TO 25);
186
-        d12 := d11(26 TO 27) & d11(0 TO 25);
187
-      END IF;
188
-      key12 := pc2( ( c12 & d12 ) );
189
-      l12 := r11;
190
-      r12 := l11 xor ( f( r11, key12 ) );
191
-      -- 11. stage
192
-      IF mode(11) = '0' THEN
193
-        c11 := c10(2 TO 27) & c10(0 TO 1);
194
-        d11 := d10(2 TO 27) & d10(0 TO 1);
195
-      ELSE
196
-        c11 := c10(26 TO 27) & c10(0 TO 25);
197
-        d11 := d10(26 TO 27) & d10(0 TO 25);
198
-      END IF;
199
-      key11 := pc2( ( c11 & d11 ) );
200
-      l11 := r10;
201
-      r11 := l10 xor ( f( r10, key11 ) );
202
-      -- 10. stage
203
-      IF mode(10) = '0' THEN
204
-        c10 := c9(2 TO 27) & c9(0 TO 1);
205
-        d10 := d9(2 TO 27) & d9(0 TO 1);
206
-      ELSE
207
-        c10 := c9(26 TO 27) & c9(0 TO 25);
208
-        d10 := d9(26 TO 27) & d9(0 TO 25);
209
-      END IF;
210
-      key10 := pc2( ( c10 & d10 ) );
211
-      l10 := r9;
212
-      r10 := l9 xor ( f( r9, key10 ) );
213
-      -- 9. stage
214
-      IF mode(9) = '0' THEN
215
-        c9 := c8(1 TO 27) & c8(0);
216
-        d9 := d8(1 TO 27) & d8(0);
217
-      ELSE
218
-        c9 := c8(27) & c8(0 TO 26);
219
-        d9 := d8(27) & d8(0 TO 26);
220
-      END IF;
221
-      key9 := pc2( ( c9 & d9 ) );
222
-      l9 := r8;
223
-      r9 := l8 xor ( f( r8, key9 ) );
224
-      -- 8. stage
225
-      IF mode(8) = '0' THEN
226
-        c8 := c7(2 TO 27) & c7(0 TO 1);
227
-        d8 := d7(2 TO 27) & d7(0 TO 1);
228
-      ELSE
229
-        c8 := c7(26 TO 27) & c7(0 TO 25);
230
-        d8 := d7(26 TO 27) & d7(0 TO 25);
231
-      END IF;
232
-      key8 := pc2( ( c8 & d8 ) );
233
-      l8 := r7;
234
-      r8 := l7 xor ( f( r7, key8 ) );
235
-      -- 7. stage
236
-      IF mode(7) = '0' THEN
237
-        c7 := c6(2 TO 27) & c6(0 TO 1);
238
-        d7 := d6(2 TO 27) & d6(0 TO 1);
239
-      ELSE
240
-        c7 := c6(26 TO 27) & c6(0 TO 25);
241
-        d7 := d6(26 TO 27) & d6(0 TO 25);
242
-      END IF;
243
-      key7 := pc2( ( c7 & d7 ) );
244
-      l7 := r6;
245
-      r7 := l6 xor ( f( r6, key7 ) );
246
-      -- 6. stage
247
-      IF mode(6) = '0' THEN
248
-        c6 := c5(2 TO 27) & c5(0 TO 1);
249
-        d6 := d5(2 TO 27) & d5(0 TO 1);
250
-      ELSE
251
-        c6 := c5(26 TO 27) & c5(0 TO 25);
252
-        d6 := d5(26 TO 27) & d5(0 TO 25);
253
-      END IF;
254
-      key6 := pc2( ( c6 & d6 ) );
255
-      l6 := r5;
256
-      r6 := l5 xor ( f( r5, key6 ) );
257
-      -- 5. stage
258
-      IF mode(5) = '0' THEN
259
-        c5 := c4(2 TO 27) & c4(0 TO 1);
260
-        d5 := d4(2 TO 27) & d4(0 TO 1);
261
-      ELSE
262
-        c5 := c4(26 TO 27) & c4(0 TO 25);
263
-        d5 := d4(26 TO 27) & d4(0 TO 25);
264
-      END IF;
265
-      key5 := pc2( ( c5 & d5 ) );
266
-      l5 := r4;
267
-      r5 := l4 xor ( f( r4, key5 ) );
268
-      -- 4. stage
269
-      IF mode(4) = '0' THEN
270
-        c4 := c3(2 TO 27) & c3(0 TO 1);
271
-        d4 := d3(2 TO 27) & d3(0 TO 1);
272
-      ELSE
273
-        c4 := c3(26 TO 27) & c3(0 TO 25);
274
-        d4 := d3(26 TO 27) & d3(0 TO 25);
275
-      END IF;
276
-      key4 := pc2( ( c4 & d4 ) );
277
-      l4 := r3;
278
-      r4 := l3 xor ( f( r3, key4 ) );
279
-      -- 3. stage
280
-      IF mode(3) = '0' THEN
281
-        c3 := c2(2 TO 27) & c2(0 TO 1);
282
-        d3 := d2(2 TO 27) & d2(0 TO 1);
283
-      ELSE
284
-        c3 := c2(26 TO 27) & c2(0 TO 25);
285
-        d3 := d2(26 TO 27) & d2(0 TO 25);
286
-      END IF;
287
-      key3 := pc2( ( c3 & d3 ) );
288
-      l3 := r2;
289
-      r3 := l2 xor ( f( r2, key3 ) );
290
-      -- 2. stage
291
-      IF mode(2) = '0' THEN
292
-        c2 := c1(1 TO 27) & c1(0);
293
-        d2 := d1(1 TO 27) & d1(0);
294
-      ELSE
295
-        c2 := c1(27) & c1(0 TO 26);
296
-        d2 := d1(27) & d1(0 TO 26);
297
-      END IF;
298
-      key2 := pc2( ( c2 & d2 ) );
299
-      l2 := r1;
300
-      r2 := l1 xor ( f( r1, key2 ) );
301
-      -- 1. stage
302
-      IF mode(1) = '0' THEN
303
-        c1 := c0(1 TO 27) & c0(0);
304
-        d1 := d0(1 TO 27) & d0(0);
305
-      ELSE
306
-        c1 := c0;
307
-        d1 := d0;
308
-      END IF;
309
-      key1 := pc2( ( c1 & d1 ) );
310
-      l1 := r0;
311
-      r1 := l0 xor ( f( r0, key1 ) );
312
-      -- input stage
313
-      l0 := ip( data_i )(0 TO 31);
314
-      r0 := ip( data_i )(32 TO 63);
315
-      c0 := pc1_c( key_i );
316
-      d0 := pc1_d( key_i );
317
-    END IF;
318
-  END PROCESS crypt;
319
-
320
-END ARCHITECTURE rtl;

+ 0
- 318
cbcdes/rtl/vhdl/des_pkg.vhd View File

@@ -1,336 +0,0 @@
1
--------------------------------------------------------------------------
2
-
3
-
4
-
5
-
6
-
7
-
8
-
9
-LIBRARY ieee;
10
-USE ieee.std_logic_1164.all;
11
-USE ieee.numeric_std.ALL;
12
-
13
-
14
-
15
-PACKAGE des_pkg IS
16
-
17
-
18
-  FUNCTION ip  ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
19
-  FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
20
-
21
-  FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector;
22
-  FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector;
23
-
24
-  FUNCTION s1 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
25
-  FUNCTION s2 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
26
-  FUNCTION s3 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
27
-  FUNCTION s4 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
28
-  FUNCTION s5 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
29
-  FUNCTION s6 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
30
-  FUNCTION s7 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
31
-  FUNCTION s8 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
32
-
33
-  FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector;
34
-
35
-  FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
36
-  FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
37
-  FUNCTION pc2   ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector;
38
-
39
-  TYPE ip_matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63;
40
-  constant ip_table : ip_matrix := (57, 49, 41, 33, 25, 17,  9, 1,
41
-                                59, 51, 43, 35, 27, 19, 11, 3,
42
-                                61, 53, 45, 37, 29, 21, 13, 5,
43
-                                63, 55, 47, 39, 31, 23, 15, 7,
44
-                                56, 48, 40, 32, 24, 16,  8, 0,
45
-                                58, 50, 42, 34, 26, 18, 10, 2,
46
-                                60, 52, 44, 36, 28, 20, 12, 4,
47
-                                62, 54, 46, 38, 30, 22, 14, 6);
48
-  constant ipn_table : ip_matrix := (39,  7, 47, 15, 55, 23, 63, 31,
49
-                                38,  6, 46, 14, 54, 22, 62, 30,
50
-                                37,  5, 45, 13, 53, 21, 61, 29,
51
-                                36,  4, 44, 12, 52, 20, 60, 28,
52
-                                35,  3, 43, 11, 51, 19, 59, 27,
53
-                                34,  2, 42, 10, 50, 18, 58, 26,
54
-                                33,  1, 41,  9, 49, 17, 57, 25,
55
-                                32,  0, 40,  8, 48, 16, 56, 24);
56
-
57
-  TYPE e_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 31;
58
-  constant e_table : e_matrix := (31,  0,  1,  2,  3,  4,
59
-                                 3,  4,  5,  6,  7,  8,
60
-                                 7,  8,  9, 10, 11, 12,
61
-                                11, 12, 13, 14, 15, 16,
62
-                                15, 16, 17, 18, 19, 20,
63
-                                19, 20, 21, 22, 23, 24,
64
-                                23, 24, 25, 26, 27, 28,
65
-                                27, 28, 29, 30, 31,  0);
66
-
67
-  TYPE s_matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15;
68
-  constant s1_table  : s_matrix := (0 => (14,  4, 13,  1,  2, 15, 11,  8,  3, 10,  6, 12,  5,  9,  0,  7),
69
-                                    1 => ( 0, 15,  7,  4, 14,  2, 13,  1, 10,  6, 12, 11,  9,  5,  3,  8),
70
-                                    2 => ( 4,  1, 14,  8, 13,  6,  2, 11, 15, 12,  9,  7,  3, 10,  5,  0),
71
-                                    3 => (15, 12,  8,  2,  4,  9,  1,  7,  5, 11,  3, 14, 10,  0,  6, 13));
72
-  constant s2_table  : s_matrix := (0 => (15,  1,  8, 14,  6, 11,  3,  4,  9,  7,  2, 13, 12,  0,  5, 10),
73
-                                    1 => ( 3, 13,  4,  7, 15,  2,  8, 14, 12,  0,  1, 10,  6,  9, 11,  5),
74
-                                    2 => ( 0, 14,  7, 11, 10,  4, 13,  1,  5,  8, 12,  6,  9,  3,  2, 15),
75
-                                    3 => (13,  8, 10,  1,  3, 15,  4,  2, 11,  6,  7, 12,  0,  5, 14,  9));
76
-  constant s3_table  : s_matrix := (0 => (10,  0,  9, 14,  6,  3, 15,  5,  1, 13, 12,  7, 11,  4,  2,  8),
77
-                                    1 => (13,  7,  0,  9,  3,  4,  6, 10,  2,  8,  5, 14, 12, 11, 15,  1),
78
-                                    2 => (13,  6,  4,  9,  8, 15,  3,  0, 11,  1,  2, 12,  5, 10, 14,  7),
79
-                                    3 => ( 1, 10, 13,  0,  6,  9,  8,  7,  4, 15, 14,  3, 11,  5,  2, 12));
80
-  constant s4_table  : s_matrix := (0 => ( 7, 13, 14,  3,  0,  6,  9, 10,  1,  2,  8,  5, 11, 12,  4,  15),
81
-                                    1 => (13,  8, 11,  5,  6, 15,  0,  3,  4,  7,  2, 12,  1, 10, 14,   9),
82
-                                    2 => (10,  6,  9,  0, 12, 11,  7, 13, 15,  1,  3, 14,  5,  2,  8,   4),
83
-                                    3 => ( 3, 15,  0,  6, 10,  1, 13,  8,  9,  4,  5, 11, 12,  7,  2,  14));
84
-  constant s5_table  : s_matrix := (0 => ( 2, 12,  4,  1,  7, 10, 11,  6,  8,  5,  3, 15, 13,  0, 14,  9),
85
-                                    1 => (14, 11,  2, 12,  4,  7, 13,  1,  5,  0, 15, 10,  3,  9,  8,  6),
86
-                                    2 => ( 4,  2,  1, 11, 10, 13,  7,  8, 15,  9, 12,  5,  6,  3,  0, 14),
87
-                                    3 => (11,  8, 12,  7,  1, 14,  2, 13,  6, 15,  0,  9, 10,  4,  5,  3));
88
-  constant s6_table  : s_matrix := (0 => (12,  1, 10, 15,  9,  2,  6,  8,  0, 13,  3,  4, 14,  7,  5, 11),
89
-                                    1 => (10, 15,  4,  2,  7, 12,  9,  5,  6,  1, 13, 14,  0, 11,  3,  8),
90
-                                    2 => ( 9, 14, 15,  5,  2,  8, 12,  3,  7,  0,  4, 10,  1, 13, 11,  6),
91
-                                    3 => ( 4,  3,  2, 12,  9,  5, 15, 10, 11, 14,  1,  7,  6,  0,  8, 13));
92
-  constant s7_table  : s_matrix := (0 => ( 4, 11,  2, 14, 15,  0,  8, 13,  3, 12,  9,  7,  5, 10,  6,  1),
93
-                                    1 => (13,  0, 11,  7,  4,  9,  1, 10, 14,  3,  5, 12,  2, 15,  8,  6),
94
-                                    2 => ( 1,  4, 11, 13, 12,  3,  7, 14, 10, 15,  6,  8,  0,  5,  9,  2),
95
-                                    3 => ( 6, 11, 13,  8,  1,  4, 10,  7,  9,  5,  0, 15, 14,  2,  3, 12));
96
-  constant s8_table  : s_matrix := (0 => (13,  2,  8,  4,  6, 15, 11,  1, 10,  9,  3, 14,  5,  0, 12,  7),
97
-                                    1 => ( 1, 15, 13,  8, 10,  3,  7,  4, 12,  5,  6, 11,  0, 14,  9,  2),
98
-                                    2 => ( 7, 11,  4,  1,  9, 12, 14,  2,  0,  6, 10, 13, 15,  3,  5,  8),
99
-                                    3 => ( 2,  1, 14,  7,  4, 10,  8, 13, 15, 12,  9,  0,  3,  5,  6, 11));
100
-
101
-  type pc_matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63;
102
-  constant pc1c_table : pc_matrix := (56, 48, 40, 32, 24, 16,  8,
103
-                                 0, 57, 49, 41, 33, 25, 17,
104
-                                 9,  1, 58, 50, 42, 34, 26,
105
-                                18, 10,  2, 59, 51, 43, 35);
106
-  constant pc1d_table : pc_matrix := (62, 54, 46, 38, 30, 22, 14,
107
-                                 6, 61, 53, 45, 37, 29, 21,
108
-                                13,  5, 60, 52, 44, 36, 28,
109
-                                20, 12,  4, 27, 19, 11,  3);
110
-
111
-  type p_matrix IS ARRAY (0 TO 31) OF natural RANGE 0 TO 31;
112
-  constant p_table : p_matrix := (15,  6, 19, 20,
113
-                                28, 11, 27, 16,
114
-                                 0, 14, 22, 25,
115
-                                 4, 17, 30,  9,
116
-                                 1,  7, 23, 13,
117
-                                31, 26,  2,  8,
118
-                                18, 12, 29,  5,
119
-                                21, 10,  3, 24);
120
-
121
-  type pc2_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 63;
122
-  constant pc2_table : pc2_matrix := (13, 16, 10, 23,  0,  4,
123
-                                 2, 27, 14,  5, 20,  9,
124
-                                22, 18, 11,  3, 25,  7,
125
-                                15,  6, 26, 19, 12,  1,
126
-                                40, 51, 30, 36, 46, 54,
127
-                                29, 39, 50, 44, 32, 47,
128
-                                43, 48, 38, 55, 33, 52,
129
-                                45, 41, 49, 35, 28, 31);
130
-
131
-
132
-END PACKAGE des_pkg;
133
-
134
-
135
-
136
-PACKAGE BODY des_pkg IS
137
-
138
-
139
-  FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
140
-    VARIABLE result : std_logic_vector(0 TO 63);
141
-  BEGIN
142
-    FOR index IN 0 TO 63 LOOP
143
-      result( index ) := input_vector( ip_table( index ) );
144
-    END LOOP;
145
-    RETURN result;
146
-  END FUNCTION ip;
147
-
148
-  FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
149
-    VARIABLE result : std_logic_vector(0 TO 63);
150
-  BEGIN
151
-    FOR index IN 0 TO 63 LOOP
152
-      result( index ) := input_vector( ipn_table( index ) );
153
-    END LOOP;
154
-    RETURN result;
155
-  END FUNCTION ipn;
156
-
157
-  FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS
158
-    VARIABLE result : std_logic_vector(0 TO 47);
159
-  BEGIN
160
-    FOR index IN 0 TO 47 LOOP
161
-      result( index ) := input_vector( e_table( index ) );
162
-    END LOOP;
163
-    RETURN result;
164
-  END FUNCTION e;
165
-
166
-  FUNCTION s1 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
167
-    VARIABLE int : std_logic_vector(0 TO 1);
168
-    VARIABLE i : integer RANGE 0 TO 3;
169
-    VARIABLE j : integer RANGE 0 TO 15;
170
-    VARIABLE result : std_logic_vector(0 TO 3);
171
-  BEGIN
172
-    int := input_vector( 0 ) & input_vector( 5 );
173
-    i := to_integer( unsigned( int ) );
174
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
175
-    result := std_logic_vector( to_unsigned( s1_table( i, j ), 4 ) );
176
-    RETURN result;
177
-  END FUNCTION s1;
178
-
179
-  FUNCTION s2 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
180
-    VARIABLE int : std_logic_vector(0 TO 1);
181
-    VARIABLE i : integer RANGE 0 TO 3;
182
-    VARIABLE j : integer RANGE 0 TO 15;
183
-    VARIABLE result : std_logic_vector(0 TO 3);
184
-  BEGIN
185
-    int := input_vector( 0 ) & input_vector( 5 );
186
-    i := to_integer( unsigned( int ) );
187
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
188
-    result := std_logic_vector( to_unsigned( s2_table( i, j ), 4 ) );
189
-    RETURN result;
190
-  END FUNCTION s2;
191
-
192
-  FUNCTION s3 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
193
-    VARIABLE int : std_logic_vector(0 TO 1);
194
-    VARIABLE i : integer RANGE 0 TO 3;
195
-    VARIABLE j : integer RANGE 0 TO 15;
196
-    VARIABLE result : std_logic_vector(0 TO 3);
197
-  BEGIN
198
-    int := input_vector( 0 ) & input_vector( 5 );
199
-    i := to_integer( unsigned( int ) );
200
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
201
-    result := std_logic_vector( to_unsigned( s3_table( i, j ), 4 ) );
202
-    RETURN result;
203
-  END FUNCTION s3;
204
-
205
-  FUNCTION s4 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
206
-    VARIABLE int : std_logic_vector(0 TO 1);
207
-    VARIABLE i : integer RANGE 0 TO 3;
208
-    VARIABLE j : integer RANGE 0 TO 15;
209
-    VARIABLE result : std_logic_vector(0 TO 3);
210
-  BEGIN
211
-    int := input_vector( 0 ) & input_vector( 5 );
212
-    i := to_integer( unsigned( int ) );
213
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
214
-    result := std_logic_vector( to_unsigned( s4_table( i, j ), 4 ) );
215
-    RETURN result;
216
-  END FUNCTION s4;
217
-
218
-  FUNCTION s5 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
219
-    VARIABLE int : std_logic_vector(0 TO 1);
220
-    VARIABLE i : integer RANGE 0 TO 3;
221
-    VARIABLE j : integer RANGE 0 TO 15;
222
-    VARIABLE result : std_logic_vector(0 TO 3);
223
-  BEGIN
224
-    int := input_vector( 0 ) & input_vector( 5 );
225
-    i := to_integer( unsigned( int ) );
226
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
227
-    result := std_logic_vector( to_unsigned( s5_table( i, j ), 4 ) );
228
-    RETURN result;
229
-  END FUNCTION s5;
230
-
231
-  FUNCTION s6 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
232
-    VARIABLE int : std_logic_vector(0 TO 1);
233
-    VARIABLE i : integer RANGE 0 TO 3;
234
-    VARIABLE j : integer RANGE 0 TO 15;
235
-    VARIABLE result : std_logic_vector(0 TO 3);
236
-  BEGIN
237
-    int := input_vector( 0 ) & input_vector( 5 );
238
-    i := to_integer( unsigned( int ) );
239
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
240
-    result := std_logic_vector( to_unsigned( s6_table( i, j ), 4 ) );
241
-    RETURN result;
242
-  END FUNCTION s6;
243
-
244
-  FUNCTION s7 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
245
-    VARIABLE int : std_logic_vector(0 TO 1);
246
-    VARIABLE i : integer RANGE 0 TO 3;
247
-    VARIABLE j : integer RANGE 0 TO 15;
248
-    VARIABLE result : std_logic_vector(0 TO 3);
249
-  BEGIN
250
-    int := input_vector( 0 ) & input_vector( 5 );
251
-    i := to_integer( unsigned( int ) );
252
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
253
-    result := std_logic_vector( to_unsigned( s7_table( i, j ), 4 ) );
254
-    RETURN result;
255
-  END FUNCTION s7;
256
-
257
-  FUNCTION s8 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
258
-    VARIABLE int : std_logic_vector(0 TO 1);
259
-    VARIABLE i : integer RANGE 0 TO 3;
260
-    VARIABLE j : integer RANGE 0 TO 15;
261
-    VARIABLE result : std_logic_vector(0 TO 3);
262
-  BEGIN
263
-    int := input_vector( 0 ) & input_vector( 5 );
264
-    i := to_integer( unsigned( int ) );
265
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
266
-    result := std_logic_vector( to_unsigned( s8_table( i, j ), 4 ) );
267
-    RETURN result;
268
-  END FUNCTION s8;
269
-
270
-  FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS
271
-    VARIABLE result : std_logic_vector(0 TO 31);
272
-  BEGIN
273
-    FOR index IN 0 TO 31 LOOP
274
-      result( index ) := input_vector( p_table( index ) );
275
-    END LOOP;
276
-    RETURN result;
277
-  END FUNCTION p;
278
-
279
-  FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector IS
280
-    VARIABLE intern : std_logic_vector(0 TO 47);
281
-    VARIABLE result : std_logic_vector(0 TO 31);
282
-  BEGIN
283
-    intern := e( input_r ) xor input_key;
284
-    result := p( s1( intern(0 TO 5) ) & s2( intern(6 TO 11) ) & s3( intern(12 TO 17) ) & s4( intern(18 TO 23) ) &
285
-              s5( intern(24 TO 29) ) & s6( intern(30 TO 35) ) & s7( intern(36 TO 41) ) & s8( intern(42 TO 47) ) );
286
-    RETURN result;
287
-  END FUNCTION f;
288
-
289
-  FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
290
-    VARIABLE result : std_logic_vector(0 TO 27);
291
-  BEGIN
292
-    FOR index IN 0 TO 27 LOOP
293
-      result( index ) := input_vector( pc1c_table( index ) );
294
-    END LOOP;
295
-    RETURN result;
296
-  END FUNCTION pc1_c;
297
-
298
-  FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
299
-
300
-    VARIABLE result : std_logic_vector(0 TO 27);
301
-  BEGIN
302
-    FOR index IN 0 TO 27 LOOP
303
-      result( index ) := input_vector( pc1d_table( index ) );
304
-    END LOOP;
305
-    RETURN result;
306
-  END FUNCTION pc1_d;
307
-
308
-  FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector IS
309
-    VARIABLE result : std_logic_vector(0 TO 47);
310
-  BEGIN
311
-    FOR index IN 0 TO 47 LOOP
312
-      result( index ) := input_vector( pc2_table( index ) );
313
-    END LOOP;
314
-    RETURN result;
315
-  END FUNCTION pc2;
316
-
317
-
318
-END PACKAGE BODY des_pkg;

cbcdes/sim/vhdl/makefile → cbcdes/sim/vhdl/Makefile View File

@@ -19,22 +19,31 @@
19 19
 # ======================================================================
20 20
 
21 21
 
22
-SRC_FILES = ../../rtl/vhdl/des_pkg.vhd ../../rtl/vhdl/des.vhd ../../rtl/vhdl/cbcdes.vhd
22
+DESIGN_NAME := cbcdes
23
+SRC_FILES   := ../../../des/rtl/vhdl/des_pkg.vhd \
24
+               ../../../des/rtl/vhdl/des.vhd \
25
+               ../../rtl/vhdl/$(DESIGN_NAME).vhd
26
+VHD_STD     := 08
23 27
 
24 28
 
25
-all : sim wave
29
+.PHONY: sim
30
+sim : tb_$(DESIGN_NAME).ghw
31
+
32
+.PHONY: all
33
+all : wave
34
+
35
+
36
+tb_$(DESIGN_NAME).o: $(SRC_FILES) tb_$(DESIGN_NAME).vhd
37
+	ghdl -a --std=$(VHD_STD) $(SRC_FILES) tb_$(DESIGN_NAME).vhd
38
+
39
+tb_$(DESIGN_NAME).ghw : tb_$(DESIGN_NAME).o
40
+	ghdl -e --std=$(VHD_STD) tb_$(DESIGN_NAME)
41
+	ghdl -r tb_$(DESIGN_NAME) --wave=tb_$(DESIGN_NAME).ghw --assert-level=error
42
+
43
+wave : tb_$(DESIGN_NAME).ghw
44
+	gtkwave -S tb_$(DESIGN_NAME).tcl tb_$(DESIGN_NAME).ghw
26 45
 
27
-sim : tb_cbcdes.ghw
28 46
 
29
-tb_cbcdes.ghw : $(SRC_FILES) tb_cbcdes.vhd
30
-	ghdl -a $(SRC_FILES) tb_cbcdes.vhd
31
-	ghdl -e tb_cbcdes
32
-	ghdl -r tb_cbcdes --wave=tb_cbcdes.ghw --assert-level=error --stop-time=220us
33
-	
34
-wave : tb_cbcdes.ghw
35
-	gtkwave -T tb_cbcdes.tcl tb_cbcdes.ghw
36
-	
37 47
 clean :
38
-	echo "# cleaning simulation files"
39
-	rm -f *.ghw
40
-	rm -f work*.cf
48
+	echo "# Cleaning files"
49
+	rm -f *.ghw *.o tb_$(DESIGN_NAME) work*.cf

+ 2
- 1
cbcdes/sim/vhdl/tb_cbcdes.tcl View File

@@ -2,12 +2,13 @@ set signals [list]
2 2
 lappend signals "top.tb_cbcdes.s_reset"
3 3
 lappend signals "top.tb_cbcdes.s_clk"
4 4
 lappend signals "top.tb_cbcdes.s_validin"
5
+lappend signals "top.tb_cbcdes.s_acceptin"
5 6
 lappend signals "top.tb_cbcdes.s_start"
6 7
 lappend signals "top.tb_cbcdes.s_mode"
7 8
 lappend signals "top.tb_cbcdes.s_key"
8 9
 lappend signals "top.tb_cbcdes.s_iv"
9 10
 lappend signals "top.tb_cbcdes.s_datain"
10 11
 lappend signals "top.tb_cbcdes.s_validout"
12
+lappend signals "top.tb_cbcdes.s_acceptout"
11 13
 lappend signals "top.tb_cbcdes.s_dataout"
12
-lappend signals "top.tb_cbcdes.s_ready"
13 14
 set num_added [ gtkwave::addSignalsFromList $signals ]

+ 36
- 46
cbcdes/sim/vhdl/tb_cbcdes.vhd View File

@@ -31,6 +31,9 @@ library ieee;
31 31
 use ieee.std_logic_1164.all;
32 32
 use ieee.numeric_std.all;
33 33
 
34
+use std.env.all;
35
+
36
+
34 37
 
35 38
 entity tb_cbcdes is
36 39
 end entity tb_cbcdes;
@@ -148,26 +151,10 @@ architecture rtl of tb_cbcdes is
148 151
   signal s_iv       : std_logic_vector(0 to 63) := (others => '0');
149 152
   signal s_datain   : std_logic_vector(0 to 63) := (others => '0');
150 153
   signal s_validin  : std_logic := '0';
151
-  signal s_ready    : std_logic := '0';
154
+  signal s_acceptin : std_logic;
152 155
   signal s_dataout  : std_logic_vector(0 to 63);
153 156
   signal s_validout : std_logic;
154
-
155
-
156
-  component cbcdes is
157
-    port (
158
-      reset_i     : in  std_logic;
159
-      clk_i       : in  std_logic;
160
-      mode_i      : in  std_logic;
161
-      start_i     : in  std_logic;
162
-      iv_i        : in  std_logic_vector(0 to 63);
163
-      key_i       : in  std_logic_vector(0 TO 63);
164
-      data_i      : in  std_logic_vector(0 TO 63);
165
-      valid_i     : in  std_logic;
166
-      ready_o     : out std_logic;
167
-      data_o      : out std_logic_vector(0 TO 63);
168
-      valid_o     : out std_logic
169
-    );
170
-  end component cbcdes;
157
+  signal s_acceptout : std_logic := '0';
171 158
 
172 159
 
173 160
 begin
@@ -188,13 +175,13 @@ begin
188 175
     s_datain  <= x"8000000000000000";
189 176
     -- Variable plaintext known answer test
190 177
     for index in c_variable_plaintext_known_answers'range loop
191
-      wait until rising_edge(s_clk) and s_ready = '1';
178
+      wait until rising_edge(s_clk);
192 179
         s_validin <= '1';
193 180
         s_start   <= '1';
194 181
         if(index /= 0) then
195 182
           s_datain <= '0' & s_datain(0 to 62);
196 183
         end if;
197
-      wait until rising_edge(s_clk);
184
+      wait until rising_edge(s_clk) and s_acceptin = '1';
198 185
         s_validin <= '0';
199 186
         s_start   <= '0';
200 187
     end loop;
@@ -209,11 +196,11 @@ begin
209 196
     -- Inverse permutation known answer test
210 197
     s_key     <= x"0101010101010101";
211 198
     for index in c_variable_plaintext_known_answers'range loop
212
-      wait until rising_edge(s_clk) and s_ready = '1';
199
+      wait until rising_edge(s_clk);
213 200
         s_validin <= '1';
214 201
         s_start   <= '1';
215 202
         s_datain  <= c_variable_plaintext_known_answers(index);
216
-      wait until rising_edge(s_clk);
203
+      wait until rising_edge(s_clk) and s_acceptin = '1';
217 204
         s_validin <= '0';
218 205
         s_start   <= '0';
219 206
     end loop;
@@ -228,7 +215,7 @@ begin
228 215
     -- Variable key known answer test
229 216
     s_key     <= x"8000000000000000";
230 217
     for index in c_variable_key_known_answers'range loop
231
-      wait until rising_edge(s_clk) and s_ready = '1';
218
+      wait until rising_edge(s_clk);
232 219
         s_validin <= '1';
233 220
         s_start   <= '1';
234 221
         if(index /= 0) then
@@ -239,7 +226,7 @@ begin
239 226
             s_key <= '0' & s_key(0 to 62);
240 227
           end if;
241 228
         end if;
242
-      wait until rising_edge(s_clk);
229
+      wait until rising_edge(s_clk) and s_acceptin = '1';
243 230
         s_validin <= '0';
244 231
         s_start   <= '0';
245 232
     end loop;
@@ -254,11 +241,11 @@ begin
254 241
     -- Permutation operation known answer test
255 242
     s_datain <= x"0000000000000000";
256 243
     for index in c_permutation_operation_known_answers_keys'range loop
257
-      wait until rising_edge(s_clk) and s_ready = '1';
244
+      wait until rising_edge(s_clk);
258 245
         s_validin <= '1';
259 246
         s_start   <= '1';
260 247
         s_key     <= c_permutation_operation_known_answers_keys(index);
261
-      wait until rising_edge(s_clk);
248
+      wait until rising_edge(s_clk) and s_acceptin = '1';
262 249
         s_validin <= '0';
263 250
         s_start   <= '0';
264 251
     end loop;
@@ -272,12 +259,12 @@ begin
272 259
     wait for 1 us;
273 260
     -- Substitution table known answer test
274 261
     for index in c_substitution_table_test_keys'range loop
275
-      wait until rising_edge(s_clk) and s_ready = '1';
262
+      wait until rising_edge(s_clk);
276 263
         s_validin <= '1';
277 264
         s_start   <= '1';
278 265
         s_key     <= c_substitution_table_test_keys(index);
279 266
         s_datain  <= c_substitution_table_test_plain(index);
280
-      wait until rising_edge(s_clk);
267
+      wait until rising_edge(s_clk) and s_acceptin = '1';
281 268
         s_validin <= '0';
282 269
         s_start   <= '0';
283 270
     end loop;
@@ -291,7 +278,7 @@ begin
291 278
     wait for 1 us;
292 279
     -- cbc known answers test
293 280
     for index in c_substitution_table_test_keys'range loop
294
-      wait until rising_edge(s_clk) and s_ready = '1';
281
+      wait until rising_edge(s_clk);
295 282
         if(index = 0) then
296 283
           s_start <= '1';
297 284
           s_key   <= x"5555555555555555";
@@ -299,7 +286,7 @@ begin
299 286
         end if;
300 287
         s_validin <= '1';
301 288
         s_datain  <= c_substitution_table_test_plain(index);
302
-      wait until rising_edge(s_clk);
289
+      wait until rising_edge(s_clk) and s_acceptin = '1';
303 290
         s_validin <= '0';
304 291
         s_start   <= '0';
305 292
     end loop;
@@ -315,12 +302,12 @@ begin
315 302
     -- Variable ciphertext known answer test
316 303
     s_key     <= x"0101010101010101";
317 304
     for index in c_variable_plaintext_known_answers'range loop
318
-      wait until rising_edge(s_clk) and s_ready = '1';
305
+      wait until rising_edge(s_clk);
319 306
         s_mode    <= '1';
320 307
         s_start   <= '1';
321 308
         s_validin <= '1';
322 309
         s_datain  <= c_variable_plaintext_known_answers(index);
323
-      wait until rising_edge(s_clk);
310
+      wait until rising_edge(s_clk) and s_acceptin = '1';
324 311
         s_validin <= '0';
325 312
         s_start   <= '0';
326 313
         s_mode    <= '0';
@@ -337,14 +324,14 @@ begin
337 324
     s_key     <= x"0101010101010101";
338 325
     s_datain  <= x"8000000000000000";
339 326
     for index in c_variable_plaintext_known_answers'range loop
340
-      wait until rising_edge(s_clk) and s_ready = '1';
327
+      wait until rising_edge(s_clk);
341 328
         s_mode    <= '1';
342 329
         s_start   <= '1';
343 330
         s_validin <= '1';
344 331
         if(index /= 0) then
345 332
           s_datain <= '0' & s_datain(0 to 62);
346 333
         end if;
347
-      wait until rising_edge(s_clk);
334
+      wait until rising_edge(s_clk) and s_acceptin = '1';
348 335
         s_validin <= '0';
349 336
         s_start   <= '0';
350 337
         s_mode    <= '0';
@@ -360,7 +347,7 @@ begin
360 347
     -- Variable key known answer test
361 348
     s_key     <= x"8000000000000000";
362 349
     for index in c_variable_key_known_answers'range loop
363
-      wait until rising_edge(s_clk) and s_ready = '1';
350
+      wait until rising_edge(s_clk);
364 351
         s_mode    <= '1';
365 352
         s_start   <= '1';
366 353
         s_validin <= '1';
@@ -373,7 +360,7 @@ begin
373 360
             s_key <= '0' & s_key(0 to 62);
374 361
           end if;
375 362
         end if;
376
-      wait until rising_edge(s_clk);
363
+      wait until rising_edge(s_clk) and s_acceptin = '1';
377 364
         s_validin <= '0';
378 365
         s_start   <= '0';
379 366
         s_mode    <= '0';
@@ -388,13 +375,13 @@ begin
388 375
     wait for 1 us;
389 376
     -- Permutation operation known answer test
390 377
     for index in c_permutation_operation_known_answers_keys'range loop
391
-      wait until rising_edge(s_clk) and s_ready = '1';
378
+      wait until rising_edge(s_clk);
392 379
         s_mode    <= '1';
393 380
         s_start   <= '1';
394 381
         s_validin <= '1';
395 382
         s_datain  <= c_permutation_operation_known_answers_cipher(index);
396 383
         s_key     <= c_permutation_operation_known_answers_keys(index);
397
-      wait until rising_edge(s_clk);
384
+      wait until rising_edge(s_clk) and s_acceptin = '1';
398 385
         s_validin <= '0';
399 386
         s_start   <= '0';
400 387
         s_mode    <= '0';
@@ -409,13 +396,13 @@ begin
409 396
     wait for 1 us;
410 397
     -- Substitution table known answer test
411 398
     for index in c_substitution_table_test_keys'range loop
412
-      wait until rising_edge(s_clk) and s_ready = '1';
399
+      wait until rising_edge(s_clk);
413 400
         s_mode    <= '1';
414 401
         s_start   <= '1';
415 402
         s_validin <= '1';
416 403
         s_key     <= c_substitution_table_test_keys(index);
417 404
         s_datain  <= c_substitution_table_test_cipher(index);
418
-      wait until rising_edge(s_clk);
405
+      wait until rising_edge(s_clk) and s_acceptin = '1';
419 406
         s_validin <= '0';
420 407
         s_start   <= '0';
421 408
         s_mode    <= '0';
@@ -430,7 +417,7 @@ begin
430 417
     wait for 1 us;
431 418
     -- cbc known answer test
432 419
     for index in c_substitution_table_test_keys'range loop
433
-      wait until rising_edge(s_clk) and s_ready = '1';
420
+      wait until rising_edge(s_clk);
434 421
         if(index = 0) then
435 422
           s_mode  <= '1';
436 423
           s_start <= '1';
@@ -439,7 +426,7 @@ begin
439 426
         end if;
440 427
         s_validin <= '1';
441 428
         s_datain  <= s_cbc_answers(index);
442
-      wait until rising_edge(s_clk);
429
+      wait until rising_edge(s_clk) and s_acceptin = '1';
443 430
         s_validin <= '0';
444 431
         s_start   <= '0';
445 432
         s_mode    <= '0';
@@ -458,6 +445,7 @@ begin
458 445
   testcheckerP : process is
459 446
     variable v_plaintext : std_logic_vector(0 to 63) := x"8000000000000000";
460 447
   begin
448
+    s_acceptout <= '1';
461 449
     report "# ENCRYPTION TESTS";
462 450
     report "# Variable plaintext known answer test";
463 451
     for index in c_variable_plaintext_known_answers'range loop
@@ -545,11 +533,12 @@ begin
545 533
           severity error;
546 534
     end loop;
547 535
     report "# Successfully passed all tests";
548
-    wait;
536
+    wait for 10 us;
537
+    stop(0);
549 538
   end process testcheckerP;
550 539
 
551 540
 
552
-  i_cbcdes : cbcdes
541
+  i_cbcdes : entity work.cbcdes
553 542
   port map (
554 543
     reset_i  => s_reset,
555 544
     clk_i    => s_clk,
@@ -559,9 +548,10 @@ begin
559 548
     iv_i     => s_iv,
560 549
     data_i   => s_datain,
561 550
     valid_i  => s_validin, 
562
-    ready_o  => s_ready,              
551
+    accept_o => s_acceptin,              
563 552
     data_o   => s_dataout,
564
-    valid_o  => s_validout
553
+    valid_o  => s_validout,
554
+    accept_i => s_acceptout
565 555
   );
566 556
 
567 557
 

+ 48
- 0
cbcdes/syn/vhdl/Makefile View File

@@ -0,0 +1,48 @@
1
+# ======================================================================
2
+# AES encryption/decryption
3
+# algorithm according to FIPS 197 specification
4
+# Copyright (C) 2020 Torsten Meissner
5
+#-----------------------------------------------------------------------
6
+# This program is free software; you can redistribute it and/or modify
7
+# it under the terms of the GNU General Public License as published by
8
+# the Free Software Foundation; either version 2 of the License, or
9
+# (at your option) any later version.
10
+
11
+# This program is distributed in the hope that it will be useful,
12
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
13
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
+# GNU General Public License for more details.
15
+
16
+# You should have received a copy of the GNU General Public License
17
+# along with this program; if not, write to the Free Software
18
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19
+# ======================================================================
20
+
21
+
22
+DESIGN_NAME := cbcdes
23
+SRC_FILES   := ../../../des/rtl/vhdl/des_pkg.vhd \
24
+               ../../../des/rtl/vhdl/des.vhd \
25
+               ../../rtl/vhdl/$(DESIGN_NAME).vhd
26
+VHD_STD     := 08
27
+
28
+
29
+.PHONY: all
30
+all : $(DESIGN_NAME)_synth.vhd syn
31
+
32
+.PHONY: syn
33
+syn: $(DESIGN_NAME).json
34
+
35
+
36
+$(DESIGN_NAME).o: $(SRC_FILES)
37
+	ghdl -a --std=$(VHD_STD) $(SRC_FILES)
38
+
39
+$(DESIGN_NAME)_synth.vhd: $(SRC_FILES)
40
+	ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@
41
+
42
+$(DESIGN_NAME).json: $(DESIGN_NAME).o
43
+	yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@'
44
+
45
+
46
+clean :
47
+	echo "# Cleaning files"
48
+	rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd