Browse Source

Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring

T. Meissner 1 week ago
parent
commit
a2c530928e

+ 62
- 4
aes/rtl/vhdl/aes.vhd View File

@@ -1,7 +1,7 @@
1 1
 -- ======================================================================
2 2
 -- AES encryption/decryption
3 3
 -- algorithm according to FIPS 197 specification
4
+-- Copyright (C) 2020 Torsten Meissner
4 5
 -------------------------------------------------------------------------
5 6
 -- This program is free software; you can redistribute it and/or modify
6 7
 -- it under the terms of the GNU General Public License as published by
@@ -34,12 +34,12 @@ entity aes is
34 34
   port (
35 35
     reset_i     : in  std_logic;                   -- async reset
36 36
     clk_i       : in  std_logic;                   -- clock
37
-    mode_i      : in  std_logic;                   -- aes-modus: 0 = encrypt, 1 = decrypt
38
-    key_i       : in  std_logic_vector(0 TO 127);  -- key input
39
-    data_i      : in  std_logic_vector(0 TO 127);  -- data input
37
+    mode_i      : in  std_logic;                   -- mode: 0 = encrypt, 1 = decrypt
38
+    key_i       : in  std_logic_vector(0 to 127);  -- key input
39
+    data_i      : in  std_logic_vector(0 to 127);  -- data input
40 40
     valid_i     : in  std_logic;                   -- input key/data valid flag
41 41
     accept_o    : out std_logic;
42
-    data_o      : out std_logic_vector(0 TO 127);  -- data output
42
+    data_o      : out std_logic_vector(0 to 127);  -- data output
43 43
     valid_o     : out std_logic;                   -- output data valid flag
44 44
     accept_i    : in  std_logic
45 45
   );
@@ -50,10 +50,67 @@ end entity aes;
50 50
 architecture rtl of aes is
51 51
 
52 52
 
53
+  signal s_mode       : std_logic;
54
+  signal s_accept_enc : std_logic;
55
+  signal s_valid_enc  : std_logic;
56
+  signal s_data_enc   : std_logic_vector(data_o'range);
57
+  signal s_accept_dec : std_logic;
58
+  signal s_valid_dec  : std_logic;
59
+  signal s_data_dec   : std_logic_vector(data_o'range);
60
+
61
+
53 62
 begin
54 63
 
55 64
 
65
+  inputregister : process (clk_i, reset_i) is
66
+  begin
67
+    if (reset_i = '0') then
68
+      s_mode  <= '0';
69
+    elsif(rising_edge(clk_i)) then
70
+      if (valid_i = '1' and accept_o = '1') then
71
+        s_mode <= mode_i;
72
+      end if;
73
+    end if;
74
+  end process inputregister;
75
+
76
+
77
+  accept_o <= s_accept_enc and s_accept_dec;
78
+  data_o   <= s_data_enc  when s_mode = '0' else s_data_dec;
79
+  valid_o  <= s_valid_enc when s_mode = '0' else s_valid_dec;
80
+
81
+
82
+  i_aes_enc : entity work.aes_enc
83
+  generic map (
84
+    design_type => design_type
85
+  )
86
+  port map (
87
+    reset_i  => reset_i,
88
+    clk_i    => clk_i,
89
+    key_i    => key_i,
90
+    data_i   => data_i,
91
+    valid_i  => valid_i and not mode_i,
92
+    accept_o => s_accept_enc,
93
+    data_o   => s_data_enc,
94
+    valid_o  => s_valid_enc,
95
+    accept_i => accept_i
96
+  );
56 97
 
57 98
 
99
+  i_aes_dec : entity work.aes_dec
100
+  generic map (
101
+    design_type => design_type
102
+  )
103
+  port map (
104
+    reset_i  => reset_i,
105
+    clk_i    => clk_i,
106
+    key_i    => key_i,
107
+    data_i   => data_i,
108
+    valid_i  => valid_i and mode_i,
109
+    accept_o => s_accept_dec,
110
+    data_o   => s_data_dec,
111
+    valid_o  => s_valid_dec,
112
+    accept_i => accept_i
113
+  );
114
+
58 115
 
59 116
 end architecture rtl;

+ 31
- 19
aes/rtl/vhdl/aes_dec.vhd View File

@@ -120,36 +120,48 @@ begin
120 120
     end process DeCryptP;
121 121
 
122 122
 
123
-    -- synthesis off
124
-    verification : block is
123
+    psl : block is
125 124
 
126
-      signal s_data : std_logic_vector(0 to 127);
125
+      signal s_key , s_din, s_dout : std_logic_vector(0 to 127) := (others => '0');
127 126
 
128 127
     begin
129 128
 
130
-      s_data <= data_o  when rising_edge(clk_i) else
131
-                128x"0" when reset_i = '0';
129
+      process (clk_i) is
130
+      begin
131
+        if (rising_edge(clk_i)) then
132
+          s_key  <= key_i;
133
+          s_din  <= data_i;
134
+          s_dout <= data_o;
135
+        end if;
136
+      end process;
132 137
 
133
-      default clock is rising_edge(Clk_i);
138
+      default clock is rising_edge(clk_i);
134 139
 
135
-      cover {accept_o};
136
-      assert always (accept_o -> s_round = 0);
140
+      -- initial reset
141
+      restrict {not reset_i; reset_i[+]}[*1];
137 142
 
138
-      cover {valid_i and accept_o};
139
-      assert always (valid_i and accept_o -> next not accept_o);
143
+      -- constraints
144
+      assume always (valid_i and not accept_o -> next valid_i);
145
+      assume always (valid_i and not accept_o -> next key_i = s_key);
146
+      assume always (valid_i and not accept_o -> next data_i = s_din);
140 147
 
141
-      cover {valid_o};
142
-      assert always (valid_o -> s_round = t_dec_rounds'high);
148
+      ACCEPTO_c : cover {accept_o};
149
+      ACCEPT_IN_ROUND_0_ONLY_a : assert always (accept_o -> s_round = 0);
143 150
 
144
-      cover {valid_o and accept_i};
145
-      assert always (valid_o and accept_i -> next not valid_o);
151
+      VALIDI_AND_ACCEPTO_c : cover {valid_i and accept_o};
152
+      ACCEPT_OFF_WHEN_VALID_a : assert always (valid_i and accept_o -> next not accept_o);
146 153
 
147
-      cover {valid_o and not accept_i};
148
-      assert always (valid_o and not accept_i -> next valid_o);
149
-      assert always (valid_o and not accept_i -> next data_o = s_data);
154
+      VALIDO_c : cover {valid_o};
155
+      VALID_IN_LAST_ROUND_ONLY_a : assert always (valid_o -> s_round = t_enc_rounds'high);
150 156
 
151
-    end block verification;
152
-    -- synthesis on
157
+      VALIDO_AND_ACCEPTI_c : cover {valid_o and accept_i};
158
+      VALID_OFF_WHEN_ACCEPTED_a : assert always (valid_o and accept_i -> next not valid_o);
159
+
160
+      VALIDO_AND_NOT_ACCEPTI_c : cover {valid_o and not accept_i};
161
+      VALID_STABLE_WHEN_NOT_ACCEPTED_a : assert always (valid_o and not accept_i -> next valid_o);
162
+      DATA_STABLE_WHEN_NOT_ACCEPTED_a : assert always (valid_o and not accept_i -> next data_o = s_dout);
163
+
164
+    end block psl;
153 165
 
154 166
 
155 167
   end generate IterG;

+ 49
- 0
aes/syn/vhdl/Makefile View File

@@ -0,0 +1,49 @@
1
+# ======================================================================
2
+# AES encryption/decryption
3
+# algorithm according to FIPS 197 specification
4
+# Copyright (C) 2020 Torsten Meissner
5
+#-----------------------------------------------------------------------
6
+# This program is free software; you can redistribute it and/or modify
7
+# it under the terms of the GNU General Public License as published by
8
+# the Free Software Foundation; either version 2 of the License, or
9
+# (at your option) any later version.
10
+
11
+# This program is distributed in the hope that it will be useful,
12
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
13
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
+# GNU General Public License for more details.
15
+
16
+# You should have received a copy of the GNU General Public License
17
+# along with this program; if not, write to the Free Software
18
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19
+# ======================================================================
20
+
21
+
22
+DESIGN_NAME := aes
23
+SRC_FILES   := ../../rtl/vhdl/aes_pkg.vhd \
24
+               ../../rtl/vhdl/aes_enc.vhd \
25
+               ../../rtl/vhdl/aes_dec.vhd \
26
+               ../../rtl/vhdl/aes.vhd
27
+VHD_STD     := 08
28
+
29
+
30
+.PHONY: all
31
+all : $(DESIGN_NAME)_synth.vhd syn
32
+
33
+.PHONY: syn
34
+syn: $(DESIGN_NAME).json
35
+
36
+
37
+$(DESIGN_NAME).o: $(SRC_FILES)
38
+	ghdl -a --std=$(VHD_STD) $(SRC_FILES)
39
+
40
+$(DESIGN_NAME)_synth.vhd: $(SRC_FILES)
41
+	ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@
42
+
43
+$(DESIGN_NAME).json: $(DESIGN_NAME).o
44
+	yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@'
45
+
46
+
47
+clean :
48
+	echo "# Cleaning files"
49
+	rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd

+ 48
- 0
cbcmac_aes/syn/vhdl/Makefile View File

@@ -0,0 +1,48 @@
1
+# ======================================================================
2
+# AES encryption/decryption
3
+# algorithm according to FIPS 197 specification
4
+# Copyright (C) 2020 Torsten Meissner
5
+#-----------------------------------------------------------------------
6
+# This program is free software; you can redistribute it and/or modify
7
+# it under the terms of the GNU General Public License as published by
8
+# the Free Software Foundation; either version 2 of the License, or
9
+# (at your option) any later version.
10
+
11
+# This program is distributed in the hope that it will be useful,
12
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
13
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
+# GNU General Public License for more details.
15
+
16
+# You should have received a copy of the GNU General Public License
17
+# along with this program; if not, write to the Free Software
18
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19
+# ======================================================================
20
+
21
+
22
+DESIGN_NAME := cbcmac_aes
23
+SRC_FILES   := ../../../aes/rtl/vhdl/aes_pkg.vhd \
24
+               ../../../aes/rtl/vhdl/aes_enc.vhd \
25
+               ../../rtl/vhdl/$(DESIGN_NAME).vhd
26
+VHD_STD     := 08
27
+
28
+
29
+.PHONY: all
30
+all : $(DESIGN_NAME)_synth.vhd syn
31
+
32
+.PHONY: syn
33
+syn: $(DESIGN_NAME).json
34
+
35
+
36
+$(DESIGN_NAME).o: $(SRC_FILES)
37
+	ghdl -a --std=$(VHD_STD) $(SRC_FILES)
38
+
39
+$(DESIGN_NAME)_synth.vhd: $(SRC_FILES)
40
+	ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@
41
+
42
+$(DESIGN_NAME).json: $(DESIGN_NAME).o
43
+	yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@'
44
+
45
+
46
+clean :
47
+	echo "# Cleaning files"
48
+	rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd

+ 48
- 0
cbcmac_des/syn/vhdl/Makefile View File

@@ -0,0 +1,48 @@
1
+# ======================================================================
2
+# CBCMAC-DES encryption/decryption
3
+# algorithm according to FIPS 46-3 specification
4
+# Copyright (C) 2020 Torsten Meissner
5
+#-----------------------------------------------------------------------
6
+# This program is free software; you can redistribute it and/or modify
7
+# it under the terms of the GNU General Public License as published by
8
+# the Free Software Foundation; either version 2 of the License, or
9
+# (at your option) any later version.
10
+
11
+# This program is distributed in the hope that it will be useful,
12
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
13
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
+# GNU General Public License for more details.
15
+
16
+# You should have received a copy of the GNU General Public License
17
+# along with this program; if not, write to the Free Software
18
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19
+# ======================================================================
20
+
21
+
22
+DESIGN_NAME      := cbcmac_des
23
+DES_SRC_FILES    := ../../../des/rtl/vhdl/des_pkg.vhd ../../../des/rtl/vhdl/des.vhd
24
+DESIGN_SRC_FILES := ../../rtl/vhdl/$(DESIGN_NAME).vhd
25
+SRC_FILES        := $(DES_SRC_FILES) $(DESIGN_SRC_FILES)
26
+VHD_STD          := 08
27
+
28
+
29
+.PHONY: all
30
+all : $(DESIGN_NAME)_synth.vhd syn
31
+
32
+.PHONY: syn
33
+syn: $(DESIGN_NAME).json
34
+
35
+
36
+$(DESIGN_NAME).o: $(SRC_FILES)
37
+	ghdl -a --std=$(VHD_STD) $(SRC_FILES)
38
+
39
+$(DESIGN_NAME)_synth.vhd: $(SRC_FILES)
40
+	ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@
41
+
42
+$(DESIGN_NAME).json: $(DESIGN_NAME).o
43
+	yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@'
44
+
45
+
46
+clean :
47
+	echo "# Cleaning files"
48
+	rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd

+ 1
- 1
ctraes/rtl/vhdl/ctraes.vhd View File

@@ -101,7 +101,7 @@ begin
101 101
   end process counterreg;
102 102
 
103 103
 
104
-  i_aes : aes_enc
104
+  i_aes_enc : entity work.aes_enc
105 105
     generic map (
106 106
       design_type => "ITER"
107 107
     )

+ 48
- 0
ctraes/syn/vhdl/Makefile View File

@@ -0,0 +1,48 @@
1
+# ======================================================================
2
+# AES encryption/decryption
3
+# algorithm according to FIPS 197 specification
4
+# Copyright (C) 2020 Torsten Meissner
5
+#-----------------------------------------------------------------------
6
+# This program is free software; you can redistribute it and/or modify
7
+# it under the terms of the GNU General Public License as published by
8
+# the Free Software Foundation; either version 2 of the License, or
9
+# (at your option) any later version.
10
+
11
+# This program is distributed in the hope that it will be useful,
12
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
13
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
+# GNU General Public License for more details.
15
+
16
+# You should have received a copy of the GNU General Public License
17
+# along with this program; if not, write to the Free Software
18
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19
+# ======================================================================
20
+
21
+
22
+DESIGN_NAME := ctraes
23
+SRC_FILES   := ../../../aes/rtl/vhdl/aes_pkg.vhd \
24
+               ../../../aes/rtl/vhdl/aes_enc.vhd \
25
+               ../../rtl/vhdl/$(DESIGN_NAME).vhd
26
+VHD_STD     := 08
27
+
28
+
29
+.PHONY: all
30
+all : $(DESIGN_NAME)_synth.vhd syn
31
+
32
+.PHONY: syn
33
+syn: $(DESIGN_NAME).json
34
+
35
+
36
+$(DESIGN_NAME).o: $(SRC_FILES)
37
+	ghdl -a --std=$(VHD_STD) $(SRC_FILES)
38
+
39
+$(DESIGN_NAME)_synth.vhd: $(SRC_FILES)
40
+	ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@
41
+
42
+$(DESIGN_NAME).json: $(DESIGN_NAME).o
43
+	yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@'
44
+
45
+
46
+clean :
47
+	echo "# Cleaning files"
48
+	rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd

+ 19
- 0
des/rtl/vhdl/des_pkg.vhd View File

@@ -29,6 +29,25 @@ library ieee;
29 29
 package des_pkg is
30 30
 
31 31
 
32
+  component des is
33
+    generic (
34
+      design_type : string := "ITER"
35
+    );
36
+    port (
37
+      reset_i     : in  std_logic;                  -- async reset
38
+      clk_i       : in  std_logic;                  -- clock
39
+      mode_i      : in  std_logic;                  -- des-modus: 0 = encrypt, 1 = decrypt
40
+      key_i       : in  std_logic_vector(0 to 63);  -- key input
41
+      data_i      : in  std_logic_vector(0 to 63);  -- data input
42
+      valid_i     : in  std_logic;                  -- input key/data valid
43
+      accept_o    : out std_logic;                  -- input accept
44
+      data_o      : out std_logic_vector(0 to 63);  -- data output
45
+      valid_o     : out std_logic;                  -- output data valid flag
46
+      accept_i    : in  std_logic                   -- output accept
47
+    );
48
+  end component des;
49
+
50
+
32 51
   type ip_matrix is array (0 to 63) of natural range 0 to 63;
33 52
   constant ip_table : ip_matrix := (57, 49, 41, 33, 25, 17,  9, 1,
34 53
                                 59, 51, 43, 35, 27, 19, 11, 3,

+ 11
- 10
des/syn/vhdl/Makefile View File

@@ -19,27 +19,28 @@
19 19
 # ======================================================================
20 20
 
21 21
 
22
-SRC_FILES := ../../rtl/vhdl/des_pkg.vhd ../../rtl/vhdl/des.vhd
23
-VHD_STD   := 08
22
+DESIGN_NAME := des
23
+SRC_FILES   := ../../../des/rtl/vhdl/$(DESIGN_NAME)_pkg.vhd ../../../des/rtl/vhdl/$(DESIGN_NAME).vhd
24
+VHD_STD     := 08
24 25
 
25 26
 
26 27
 .PHONY: all
27
-all: des_synth.vhd syn
28
+all : $(DESIGN_NAME)_synth.vhd syn
28 29
 
29 30
 .PHONY: syn
30
-syn: des.json
31
+syn: $(DESIGN_NAME).json
31 32
 
32 33
 
33
-des.o: $(SRC_FILES)
34
+$(DESIGN_NAME).o: $(SRC_FILES)
34 35
 	ghdl -a --std=$(VHD_STD) $(SRC_FILES)
35 36
 
36
-des_synth.vhd: $(SRC_FILES)
37
-	ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e des > $@
37
+$(DESIGN_NAME)_synth.vhd: $(SRC_FILES)
38
+	ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@
38 39
 
39
-des.json: des.o
40
-	yosys -m ghdl -p 'ghdl --std=08 --no-formal des; synth_ice40 -json $@'
40
+$(DESIGN_NAME).json: $(DESIGN_NAME).o
41
+	yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@'
41 42
 
42 43
 
43 44
 clean :
44 45
 	echo "# Cleaning files"
45
-	rm -f *.o work*.cf des.json des_synth.vhd
46
+	rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd

+ 0
- 320
tdes/rtl/vhdl/des.vhd View File

@@ -1,340 +0,0 @@
1
--------------------------------------------------------------------------
2
-
3
-
4
-
5
-
6
-
7
-
8
-LIBRARY ieee;
9
-USE ieee.std_logic_1164.all;
10
-USE ieee.numeric_std.ALL;
11
-USE work.des_pkg.ALL;
12
-
13
-
14
-ENTITY des IS
15
-  PORT (
16
-    reset_i     : in  std_logic;                  -- async reset
17
-    clk_i       : IN  std_logic;                  -- clock
18
-    mode_i      : IN  std_logic;                  -- des-modus: 0 = encrypt, 1 = decrypt
19
-    key_i       : IN  std_logic_vector(0 TO 63);  -- key input
20
-    data_i      : IN  std_logic_vector(0 TO 63);  -- data input
21
-    valid_i     : IN  std_logic;                  -- input key/data valid flag
22
-    data_o      : OUT std_logic_vector(0 TO 63);  -- data output
23
-    valid_o     : OUT std_logic                   -- output data valid flag
24
-  );
25
-END ENTITY des;
26
-
27
-
28
-ARCHITECTURE rtl OF des IS
29
-
30
-BEGIN
31
-
32
-  crypt : PROCESS ( clk_i ) IS
33
-    -- variables for key calculation
34
-    VARIABLE c0  : std_logic_vector(0 TO 27) := (others => '0');
35
-    VARIABLE c1  : std_logic_vector(0 TO 27) := (others => '0');
36
-    VARIABLE c2  : std_logic_vector(0 TO 27) := (others => '0');
37
-    VARIABLE c3  : std_logic_vector(0 TO 27) := (others => '0');
38
-    VARIABLE c4  : std_logic_vector(0 TO 27) := (others => '0');
39
-    VARIABLE c5  : std_logic_vector(0 TO 27) := (others => '0');
40
-    VARIABLE c6  : std_logic_vector(0 TO 27) := (others => '0');
41
-    VARIABLE c7  : std_logic_vector(0 TO 27) := (others => '0');
42
-    VARIABLE c8  : std_logic_vector(0 TO 27) := (others => '0');
43
-    VARIABLE c9  : std_logic_vector(0 TO 27) := (others => '0');
44
-    VARIABLE c10 : std_logic_vector(0 TO 27) := (others => '0');
45
-    VARIABLE c11 : std_logic_vector(0 TO 27) := (others => '0');
46
-    VARIABLE c12 : std_logic_vector(0 TO 27) := (others => '0');
47
-    VARIABLE c13 : std_logic_vector(0 TO 27) := (others => '0');
48
-    VARIABLE c14 : std_logic_vector(0 TO 27) := (others => '0');
49
-    VARIABLE c15 : std_logic_vector(0 TO 27) := (others => '0');
50
-    VARIABLE c16 : std_logic_vector(0 TO 27) := (others => '0');
51
-    VARIABLE d0  : std_logic_vector(0 TO 27) := (others => '0');
52
-    VARIABLE d1  : std_logic_vector(0 TO 27) := (others => '0');
53
-    VARIABLE d2  : std_logic_vector(0 TO 27) := (others => '0');
54
-    VARIABLE d3  : std_logic_vector(0 TO 27) := (others => '0');
55
-    VARIABLE d4  : std_logic_vector(0 TO 27) := (others => '0');
56
-    VARIABLE d5  : std_logic_vector(0 TO 27) := (others => '0');
57
-    VARIABLE d6  : std_logic_vector(0 TO 27) := (others => '0');
58
-    VARIABLE d7  : std_logic_vector(0 TO 27) := (others => '0');
59
-    VARIABLE d8  : std_logic_vector(0 TO 27) := (others => '0');
60
-    VARIABLE d9  : std_logic_vector(0 TO 27) := (others => '0');
61
-    VARIABLE d10 : std_logic_vector(0 TO 27) := (others => '0');
62
-    VARIABLE d11 : std_logic_vector(0 TO 27) := (others => '0');
63
-    VARIABLE d12 : std_logic_vector(0 TO 27) := (others => '0');
64
-    VARIABLE d13 : std_logic_vector(0 TO 27) := (others => '0');
65
-    VARIABLE d14 : std_logic_vector(0 TO 27) := (others => '0');
66
-    VARIABLE d15 : std_logic_vector(0 TO 27) := (others => '0');
67
-    VARIABLE d16 : std_logic_vector(0 TO 27) := (others => '0');
68
-    -- key variables
69
-    VARIABLE key1  : std_logic_vector(0 TO 47) := (others => '0');
70
-    VARIABLE key2  : std_logic_vector(0 TO 47) := (others => '0');
71
-    VARIABLE key3  : std_logic_vector(0 TO 47) := (others => '0');
72
-    VARIABLE key4  : std_logic_vector(0 TO 47) := (others => '0');
73
-    VARIABLE key5  : std_logic_vector(0 TO 47) := (others => '0');
74
-    VARIABLE key6  : std_logic_vector(0 TO 47) := (others => '0');
75
-    VARIABLE key7  : std_logic_vector(0 TO 47) := (others => '0');
76
-    VARIABLE key8  : std_logic_vector(0 TO 47) := (others => '0');
77
-    VARIABLE key9  : std_logic_vector(0 TO 47) := (others => '0');
78
-    VARIABLE key10 : std_logic_vector(0 TO 47) := (others => '0');
79
-    VARIABLE key11 : std_logic_vector(0 TO 47) := (others => '0');
80
-    VARIABLE key12 : std_logic_vector(0 TO 47) := (others => '0');
81
-    VARIABLE key13 : std_logic_vector(0 TO 47) := (others => '0');
82
-    VARIABLE key14 : std_logic_vector(0 TO 47) := (others => '0');
83
-    VARIABLE key15 : std_logic_vector(0 TO 47) := (others => '0');
84
-    VARIABLE key16 : std_logic_vector(0 TO 47) := (others => '0');
85
-    -- variables for left & right data blocks
86
-    VARIABLE l0  : std_logic_vector( 0 TO 31) := (others => '0');
87
-    VARIABLE l1  : std_logic_vector( 0 TO 31) := (others => '0');
88
-    VARIABLE l2  : std_logic_vector( 0 TO 31) := (others => '0');
89
-    VARIABLE l3  : std_logic_vector( 0 TO 31) := (others => '0');
90
-    VARIABLE l4  : std_logic_vector( 0 TO 31) := (others => '0');
91
-    VARIABLE l5  : std_logic_vector( 0 TO 31) := (others => '0');
92
-    VARIABLE l6  : std_logic_vector( 0 TO 31) := (others => '0');
93
-    VARIABLE l7  : std_logic_vector( 0 TO 31) := (others => '0');
94
-    VARIABLE l8  : std_logic_vector( 0 TO 31) := (others => '0');
95
-    VARIABLE l9  : std_logic_vector( 0 TO 31) := (others => '0');
96
-    VARIABLE l10 : std_logic_vector( 0 TO 31) := (others => '0');
97
-    VARIABLE l11 : std_logic_vector( 0 TO 31) := (others => '0');
98
-    VARIABLE l12 : std_logic_vector( 0 TO 31) := (others => '0');
99
-    VARIABLE l13 : std_logic_vector( 0 TO 31) := (others => '0');
100
-    VARIABLE l14 : std_logic_vector( 0 TO 31) := (others => '0');
101
-    VARIABLE l15 : std_logic_vector( 0 TO 31) := (others => '0');
102
-    VARIABLE l16 : std_logic_vector( 0 TO 31) := (others => '0');
103
-    VARIABLE r0  : std_logic_vector( 0 TO 31) := (others => '0');
104
-    VARIABLE r1  : std_logic_vector( 0 TO 31) := (others => '0');
105
-    VARIABLE r2  : std_logic_vector( 0 TO 31) := (others => '0');
106
-    VARIABLE r3  : std_logic_vector( 0 TO 31) := (others => '0');
107
-    VARIABLE r4  : std_logic_vector( 0 TO 31) := (others => '0');
108
-    VARIABLE r5  : std_logic_vector( 0 TO 31) := (others => '0');
109
-    VARIABLE r6  : std_logic_vector( 0 TO 31) := (others => '0');
110
-    VARIABLE r7  : std_logic_vector( 0 TO 31) := (others => '0');
111
-    VARIABLE r8  : std_logic_vector( 0 TO 31) := (others => '0');
112
-    VARIABLE r9  : std_logic_vector( 0 TO 31) := (others => '0');
113
-    VARIABLE r10 : std_logic_vector( 0 TO 31) := (others => '0');
114
-    VARIABLE r11 : std_logic_vector( 0 TO 31) := (others => '0');
115
-    VARIABLE r12 : std_logic_vector( 0 TO 31) := (others => '0');
116
-    VARIABLE r13 : std_logic_vector( 0 TO 31) := (others => '0');
117
-    VARIABLE r14 : std_logic_vector( 0 TO 31) := (others => '0');
118
-    VARIABLE r15 : std_logic_vector( 0 TO 31) := (others => '0');
119
-    VARIABLE r16 : std_logic_vector( 0 TO 31) := (others => '0');
120
-    -- variables for mode & valid shift registers
121
-    VARIABLE mode  : std_logic_vector(0 TO 16) := (others => '0');
122
-    VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0');
123
-  BEGIN
124
-    if(reset_i = '0') then
125
-      data_o  <= (others => '0');
126
-      valid_o <= '0';
127
-    elsif rising_edge( clk_i ) THEN
128
-      -- shift registers
129
-      valid(1 TO 17) := valid(0 TO 16);
130
-      valid(0) := valid_i;
131
-      mode(1 TO 16) := mode(0 TO 15);
132
-      mode(0)  := mode_i;
133
-      -- output stage
134
-      valid_o <= valid(17);
135
-      data_o  <= ipn( ( r16 & l16 ) );
136
-      -- 16. stage
137
-      IF mode(16) = '0' THEN
138
-        c16 := c15(1 TO 27) & c15(0);
139
-        d16 := d15(1 TO 27) & d15(0);
140
-      ELSE
141
-        c16 := c15(27) & c15(0 TO 26);
142
-        d16 := d15(27) & d15(0 TO 26);
143
-      END IF;
144
-      key16 := pc2( ( c16 & d16 ) );
145
-      l16 := r15;
146
-      r16 := l15 xor ( f( r15, key16 ) );
147
-      -- 15. stage
148
-      IF mode(15) = '0' THEN
149
-        c15 := c14(2 TO 27) & c14(0 TO 1);
150
-        d15 := d14(2 TO 27) & d14(0 TO 1);
151
-      ELSE
152
-        c15 := c14(26 TO 27) & c14(0 TO 25);
153
-        d15 := d14(26 TO 27) & d14(0 TO 25);
154
-      END IF;
155
-      key15 := pc2( ( c15 & d15 ) );
156
-      l15 := r14;
157
-      r15 := l14 xor ( f( r14, key15 ) );
158
-      -- 14. stage
159
-      IF mode(14) = '0' THEN
160
-        c14 := c13(2 TO 27) & c13(0 TO 1);
161
-        d14 := d13(2 TO 27) & d13(0 TO 1);
162
-      ELSE
163
-        c14 := c13(26 TO 27) & c13(0 TO 25);
164
-        d14 := d13(26 TO 27) & d13(0 TO 25);
165
-      END IF;
166
-      key14 := pc2( ( c14 & d14 ) );
167
-      l14 := r13;
168
-      r14 := l13 xor ( f( r13, key14 ) );
169
-      -- 13. stage
170
-      IF mode(13) = '0' THEN
171
-        c13 := c12(2 TO 27) & c12(0 TO 1);
172
-        d13 := d12(2 TO 27) & d12(0 TO 1);
173
-      ELSE
174
-        c13 := c12(26 TO 27) & c12(0 TO 25);
175
-        d13 := d12(26 TO 27) & d12(0 TO 25);
176
-      END IF;
177
-      key13 := pc2( ( c13 & d13 ) );
178
-      l13 := r12;
179
-      r13 := l12 xor ( f( r12, key13 ) );
180
-      -- 12. stage
181
-      IF mode(12) = '0' THEN
182
-        c12 := c11(2 TO 27) & c11(0 TO 1);
183
-        d12 := d11(2 TO 27) & d11(0 TO 1);
184
-      ELSE
185
-        c12 := c11(26 TO 27) & c11(0 TO 25);
186
-        d12 := d11(26 TO 27) & d11(0 TO 25);
187
-      END IF;
188
-      key12 := pc2( ( c12 & d12 ) );
189
-      l12 := r11;
190
-      r12 := l11 xor ( f( r11, key12 ) );
191
-      -- 11. stage
192
-      IF mode(11) = '0' THEN
193
-        c11 := c10(2 TO 27) & c10(0 TO 1);
194
-        d11 := d10(2 TO 27) & d10(0 TO 1);
195
-      ELSE
196
-        c11 := c10(26 TO 27) & c10(0 TO 25);
197
-        d11 := d10(26 TO 27) & d10(0 TO 25);
198
-      END IF;
199
-      key11 := pc2( ( c11 & d11 ) );
200
-      l11 := r10;
201
-      r11 := l10 xor ( f( r10, key11 ) );
202
-      -- 10. stage
203
-      IF mode(10) = '0' THEN
204
-        c10 := c9(2 TO 27) & c9(0 TO 1);
205
-        d10 := d9(2 TO 27) & d9(0 TO 1);
206
-      ELSE
207
-        c10 := c9(26 TO 27) & c9(0 TO 25);
208
-        d10 := d9(26 TO 27) & d9(0 TO 25);
209
-      END IF;
210
-      key10 := pc2( ( c10 & d10 ) );
211
-      l10 := r9;
212
-      r10 := l9 xor ( f( r9, key10 ) );
213
-      -- 9. stage
214
-      IF mode(9) = '0' THEN
215
-        c9 := c8(1 TO 27) & c8(0);
216
-        d9 := d8(1 TO 27) & d8(0);
217
-      ELSE
218
-        c9 := c8(27) & c8(0 TO 26);
219
-        d9 := d8(27) & d8(0 TO 26);
220
-      END IF;
221
-      key9 := pc2( ( c9 & d9 ) );
222
-      l9 := r8;
223
-      r9 := l8 xor ( f( r8, key9 ) );
224
-      -- 8. stage
225
-      IF mode(8) = '0' THEN
226
-        c8 := c7(2 TO 27) & c7(0 TO 1);
227
-        d8 := d7(2 TO 27) & d7(0 TO 1);
228
-      ELSE
229
-        c8 := c7(26 TO 27) & c7(0 TO 25);
230
-        d8 := d7(26 TO 27) & d7(0 TO 25);
231
-      END IF;
232
-      key8 := pc2( ( c8 & d8 ) );
233
-      l8 := r7;
234
-      r8 := l7 xor ( f( r7, key8 ) );
235
-      -- 7. stage
236
-      IF mode(7) = '0' THEN
237
-        c7 := c6(2 TO 27) & c6(0 TO 1);
238
-        d7 := d6(2 TO 27) & d6(0 TO 1);
239
-      ELSE
240
-        c7 := c6(26 TO 27) & c6(0 TO 25);
241
-        d7 := d6(26 TO 27) & d6(0 TO 25);
242
-      END IF;
243
-      key7 := pc2( ( c7 & d7 ) );
244
-      l7 := r6;
245
-      r7 := l6 xor ( f( r6, key7 ) );
246
-      -- 6. stage
247
-      IF mode(6) = '0' THEN
248
-        c6 := c5(2 TO 27) & c5(0 TO 1);
249
-        d6 := d5(2 TO 27) & d5(0 TO 1);
250
-      ELSE
251
-        c6 := c5(26 TO 27) & c5(0 TO 25);
252
-        d6 := d5(26 TO 27) & d5(0 TO 25);
253
-      END IF;
254
-      key6 := pc2( ( c6 & d6 ) );
255
-      l6 := r5;
256
-      r6 := l5 xor ( f( r5, key6 ) );
257
-      -- 5. stage
258
-      IF mode(5) = '0' THEN
259
-        c5 := c4(2 TO 27) & c4(0 TO 1);
260
-        d5 := d4(2 TO 27) & d4(0 TO 1);
261
-      ELSE
262
-        c5 := c4(26 TO 27) & c4(0 TO 25);
263
-        d5 := d4(26 TO 27) & d4(0 TO 25);
264
-      END IF;
265
-      key5 := pc2( ( c5 & d5 ) );
266
-      l5 := r4;
267
-      r5 := l4 xor ( f( r4, key5 ) );
268
-      -- 4. stage
269
-      IF mode(4) = '0' THEN
270
-        c4 := c3(2 TO 27) & c3(0 TO 1);
271
-        d4 := d3(2 TO 27) & d3(0 TO 1);
272
-      ELSE
273
-        c4 := c3(26 TO 27) & c3(0 TO 25);
274
-        d4 := d3(26 TO 27) & d3(0 TO 25);
275
-      END IF;
276
-      key4 := pc2( ( c4 & d4 ) );
277
-      l4 := r3;
278
-      r4 := l3 xor ( f( r3, key4 ) );
279
-      -- 3. stage
280
-      IF mode(3) = '0' THEN
281
-        c3 := c2(2 TO 27) & c2(0 TO 1);
282
-        d3 := d2(2 TO 27) & d2(0 TO 1);
283
-      ELSE
284
-        c3 := c2(26 TO 27) & c2(0 TO 25);
285
-        d3 := d2(26 TO 27) & d2(0 TO 25);
286
-      END IF;
287
-      key3 := pc2( ( c3 & d3 ) );
288
-      l3 := r2;
289
-      r3 := l2 xor ( f( r2, key3 ) );
290
-      -- 2. stage
291
-      IF mode(2) = '0' THEN
292
-        c2 := c1(1 TO 27) & c1(0);
293
-        d2 := d1(1 TO 27) & d1(0);
294
-      ELSE
295
-        c2 := c1(27) & c1(0 TO 26);
296
-        d2 := d1(27) & d1(0 TO 26);
297
-      END IF;
298
-      key2 := pc2( ( c2 & d2 ) );
299
-      l2 := r1;
300
-      r2 := l1 xor ( f( r1, key2 ) );
301
-      -- 1. stage
302
-      IF mode(1) = '0' THEN
303
-        c1 := c0(1 TO 27) & c0(0);
304
-        d1 := d0(1 TO 27) & d0(0);
305
-      ELSE
306
-        c1 := c0;
307
-        d1 := d0;
308
-      END IF;
309
-      key1 := pc2( ( c1 & d1 ) );
310
-      l1 := r0;
311
-      r1 := l0 xor ( f( r0, key1 ) );
312
-      -- input stage
313
-      l0 := ip( data_i )(0 TO 31);
314
-      r0 := ip( data_i )(32 TO 63);
315
-      c0 := pc1_c( key_i );
316
-      d0 := pc1_d( key_i );
317
-    END IF;
318
-  END PROCESS crypt;
319
-
320
-END ARCHITECTURE rtl;

+ 0
- 318
tdes/rtl/vhdl/des_pkg.vhd View File

@@ -1,336 +0,0 @@
1
--------------------------------------------------------------------------
2
-
3
-
4
-
5
-
6
-
7
-
8
-
9
-LIBRARY ieee;
10
-USE ieee.std_logic_1164.all;
11
-USE ieee.numeric_std.ALL;
12
-
13
-
14
-
15
-PACKAGE des_pkg IS
16
-
17
-
18
-  FUNCTION ip  ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
19
-  FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
20
-
21
-  FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector;
22
-  FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector;
23
-
24
-  FUNCTION s1 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
25
-  FUNCTION s2 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
26
-  FUNCTION s3 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
27
-  FUNCTION s4 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
28
-  FUNCTION s5 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
29
-  FUNCTION s6 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
30
-  FUNCTION s7 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
31
-  FUNCTION s8 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
32
-
33
-  FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector;
34
-
35
-  FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
36
-  FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
37
-  FUNCTION pc2   ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector;
38
-
39
-  TYPE ip_matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63;
40
-  constant ip_table : ip_matrix := (57, 49, 41, 33, 25, 17,  9, 1,
41
-                                59, 51, 43, 35, 27, 19, 11, 3,
42
-                                61, 53, 45, 37, 29, 21, 13, 5,
43
-                                63, 55, 47, 39, 31, 23, 15, 7,
44
-                                56, 48, 40, 32, 24, 16,  8, 0,
45
-                                58, 50, 42, 34, 26, 18, 10, 2,
46
-                                60, 52, 44, 36, 28, 20, 12, 4,
47
-                                62, 54, 46, 38, 30, 22, 14, 6);
48
-  constant ipn_table : ip_matrix := (39,  7, 47, 15, 55, 23, 63, 31,
49
-                                38,  6, 46, 14, 54, 22, 62, 30,
50
-                                37,  5, 45, 13, 53, 21, 61, 29,
51
-                                36,  4, 44, 12, 52, 20, 60, 28,
52
-                                35,  3, 43, 11, 51, 19, 59, 27,
53
-                                34,  2, 42, 10, 50, 18, 58, 26,
54
-                                33,  1, 41,  9, 49, 17, 57, 25,
55
-                                32,  0, 40,  8, 48, 16, 56, 24);
56
-
57
-  TYPE e_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 31;
58
-  constant e_table : e_matrix := (31,  0,  1,  2,  3,  4,
59
-                                 3,  4,  5,  6,  7,  8,
60
-                                 7,  8,  9, 10, 11, 12,
61
-                                11, 12, 13, 14, 15, 16,
62
-                                15, 16, 17, 18, 19, 20,
63
-                                19, 20, 21, 22, 23, 24,
64
-                                23, 24, 25, 26, 27, 28,
65
-                                27, 28, 29, 30, 31,  0);
66
-
67
-  TYPE s_matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15;
68
-  constant s1_table  : s_matrix := (0 => (14,  4, 13,  1,  2, 15, 11,  8,  3, 10,  6, 12,  5,  9,  0,  7),
69
-                                    1 => ( 0, 15,  7,  4, 14,  2, 13,  1, 10,  6, 12, 11,  9,  5,  3,  8),
70
-                                    2 => ( 4,  1, 14,  8, 13,  6,  2, 11, 15, 12,  9,  7,  3, 10,  5,  0),
71
-                                    3 => (15, 12,  8,  2,  4,  9,  1,  7,  5, 11,  3, 14, 10,  0,  6, 13));
72
-  constant s2_table  : s_matrix := (0 => (15,  1,  8, 14,  6, 11,  3,  4,  9,  7,  2, 13, 12,  0,  5, 10),
73
-                                    1 => ( 3, 13,  4,  7, 15,  2,  8, 14, 12,  0,  1, 10,  6,  9, 11,  5),
74
-                                    2 => ( 0, 14,  7, 11, 10,  4, 13,  1,  5,  8, 12,  6,  9,  3,  2, 15),
75
-                                    3 => (13,  8, 10,  1,  3, 15,  4,  2, 11,  6,  7, 12,  0,  5, 14,  9));
76
-  constant s3_table  : s_matrix := (0 => (10,  0,  9, 14,  6,  3, 15,  5,  1, 13, 12,  7, 11,  4,  2,  8),
77
-                                    1 => (13,  7,  0,  9,  3,  4,  6, 10,  2,  8,  5, 14, 12, 11, 15,  1),
78
-                                    2 => (13,  6,  4,  9,  8, 15,  3,  0, 11,  1,  2, 12,  5, 10, 14,  7),
79
-                                    3 => ( 1, 10, 13,  0,  6,  9,  8,  7,  4, 15, 14,  3, 11,  5,  2, 12));
80
-  constant s4_table  : s_matrix := (0 => ( 7, 13, 14,  3,  0,  6,  9, 10,  1,  2,  8,  5, 11, 12,  4,  15),
81
-                                    1 => (13,  8, 11,  5,  6, 15,  0,  3,  4,  7,  2, 12,  1, 10, 14,   9),
82
-                                    2 => (10,  6,  9,  0, 12, 11,  7, 13, 15,  1,  3, 14,  5,  2,  8,   4),
83
-                                    3 => ( 3, 15,  0,  6, 10,  1, 13,  8,  9,  4,  5, 11, 12,  7,  2,  14));
84
-  constant s5_table  : s_matrix := (0 => ( 2, 12,  4,  1,  7, 10, 11,  6,  8,  5,  3, 15, 13,  0, 14,  9),
85
-                                    1 => (14, 11,  2, 12,  4,  7, 13,  1,  5,  0, 15, 10,  3,  9,  8,  6),
86
-                                    2 => ( 4,  2,  1, 11, 10, 13,  7,  8, 15,  9, 12,  5,  6,  3,  0, 14),
87
-                                    3 => (11,  8, 12,  7,  1, 14,  2, 13,  6, 15,  0,  9, 10,  4,  5,  3));
88
-  constant s6_table  : s_matrix := (0 => (12,  1, 10, 15,  9,  2,  6,  8,  0, 13,  3,  4, 14,  7,  5, 11),
89
-                                    1 => (10, 15,  4,  2,  7, 12,  9,  5,  6,  1, 13, 14,  0, 11,  3,  8),
90
-                                    2 => ( 9, 14, 15,  5,  2,  8, 12,  3,  7,  0,  4, 10,  1, 13, 11,  6),
91
-                                    3 => ( 4,  3,  2, 12,  9,  5, 15, 10, 11, 14,  1,  7,  6,  0,  8, 13));
92
-  constant s7_table  : s_matrix := (0 => ( 4, 11,  2, 14, 15,  0,  8, 13,  3, 12,  9,  7,  5, 10,  6,  1),
93
-                                    1 => (13,  0, 11,  7,  4,  9,  1, 10, 14,  3,  5, 12,  2, 15,  8,  6),
94
-                                    2 => ( 1,  4, 11, 13, 12,  3,  7, 14, 10, 15,  6,  8,  0,  5,  9,  2),
95
-                                    3 => ( 6, 11, 13,  8,  1,  4, 10,  7,  9,  5,  0, 15, 14,  2,  3, 12));
96
-  constant s8_table  : s_matrix := (0 => (13,  2,  8,  4,  6, 15, 11,  1, 10,  9,  3, 14,  5,  0, 12,  7),
97
-                                    1 => ( 1, 15, 13,  8, 10,  3,  7,  4, 12,  5,  6, 11,  0, 14,  9,  2),
98
-                                    2 => ( 7, 11,  4,  1,  9, 12, 14,  2,  0,  6, 10, 13, 15,  3,  5,  8),
99
-                                    3 => ( 2,  1, 14,  7,  4, 10,  8, 13, 15, 12,  9,  0,  3,  5,  6, 11));
100
-
101
-  type pc_matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63;
102
-  constant pc1c_table : pc_matrix := (56, 48, 40, 32, 24, 16,  8,
103
-                                 0, 57, 49, 41, 33, 25, 17,
104
-                                 9,  1, 58, 50, 42, 34, 26,
105
-                                18, 10,  2, 59, 51, 43, 35);
106
-  constant pc1d_table : pc_matrix := (62, 54, 46, 38, 30, 22, 14,
107
-                                 6, 61, 53, 45, 37, 29, 21,
108
-                                13,  5, 60, 52, 44, 36, 28,
109
-                                20, 12,  4, 27, 19, 11,  3);
110
-
111
-  type p_matrix IS ARRAY (0 TO 31) OF natural RANGE 0 TO 31;
112
-  constant p_table : p_matrix := (15,  6, 19, 20,
113
-                                28, 11, 27, 16,
114
-                                 0, 14, 22, 25,
115
-                                 4, 17, 30,  9,
116
-                                 1,  7, 23, 13,
117
-                                31, 26,  2,  8,
118
-                                18, 12, 29,  5,
119
-                                21, 10,  3, 24);
120
-
121
-  type pc2_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 63;
122
-  constant pc2_table : pc2_matrix := (13, 16, 10, 23,  0,  4,
123
-                                 2, 27, 14,  5, 20,  9,
124
-                                22, 18, 11,  3, 25,  7,
125
-                                15,  6, 26, 19, 12,  1,
126
-                                40, 51, 30, 36, 46, 54,
127
-                                29, 39, 50, 44, 32, 47,
128
-                                43, 48, 38, 55, 33, 52,
129
-                                45, 41, 49, 35, 28, 31);
130
-
131
-
132
-END PACKAGE des_pkg;
133
-
134
-
135
-
136
-PACKAGE BODY des_pkg IS
137
-
138
-
139
-  FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
140
-    VARIABLE result : std_logic_vector(0 TO 63);
141
-  BEGIN
142
-    FOR index IN 0 TO 63 LOOP
143
-      result( index ) := input_vector( ip_table( index ) );
144
-    END LOOP;
145
-    RETURN result;
146
-  END FUNCTION ip;
147
-
148
-  FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
149
-    VARIABLE result : std_logic_vector(0 TO 63);
150
-  BEGIN
151
-    FOR index IN 0 TO 63 LOOP
152
-      result( index ) := input_vector( ipn_table( index ) );
153
-    END LOOP;
154
-    RETURN result;
155
-  END FUNCTION ipn;
156
-
157
-  FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS
158
-    VARIABLE result : std_logic_vector(0 TO 47);
159
-  BEGIN
160
-    FOR index IN 0 TO 47 LOOP
161
-      result( index ) := input_vector( e_table( index ) );
162
-    END LOOP;
163
-    RETURN result;
164
-  END FUNCTION e;
165
-
166
-  FUNCTION s1 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
167
-    VARIABLE int : std_logic_vector(0 TO 1);
168
-    VARIABLE i : integer RANGE 0 TO 3;
169
-    VARIABLE j : integer RANGE 0 TO 15;
170
-    VARIABLE result : std_logic_vector(0 TO 3);
171
-  BEGIN
172
-    int := input_vector( 0 ) & input_vector( 5 );
173
-    i := to_integer( unsigned( int ) );
174
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
175
-    result := std_logic_vector( to_unsigned( s1_table( i, j ), 4 ) );
176
-    RETURN result;
177
-  END FUNCTION s1;
178
-
179
-  FUNCTION s2 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
180
-    VARIABLE int : std_logic_vector(0 TO 1);
181
-    VARIABLE i : integer RANGE 0 TO 3;
182
-    VARIABLE j : integer RANGE 0 TO 15;
183
-    VARIABLE result : std_logic_vector(0 TO 3);
184
-  BEGIN
185
-    int := input_vector( 0 ) & input_vector( 5 );
186
-    i := to_integer( unsigned( int ) );
187
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
188
-    result := std_logic_vector( to_unsigned( s2_table( i, j ), 4 ) );
189
-    RETURN result;
190
-  END FUNCTION s2;
191
-
192
-  FUNCTION s3 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
193
-    VARIABLE int : std_logic_vector(0 TO 1);
194
-    VARIABLE i : integer RANGE 0 TO 3;
195
-    VARIABLE j : integer RANGE 0 TO 15;
196
-    VARIABLE result : std_logic_vector(0 TO 3);
197
-  BEGIN
198
-    int := input_vector( 0 ) & input_vector( 5 );
199
-    i := to_integer( unsigned( int ) );
200
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
201
-    result := std_logic_vector( to_unsigned( s3_table( i, j ), 4 ) );
202
-    RETURN result;
203
-  END FUNCTION s3;
204
-
205
-  FUNCTION s4 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
206
-    VARIABLE int : std_logic_vector(0 TO 1);
207
-    VARIABLE i : integer RANGE 0 TO 3;
208
-    VARIABLE j : integer RANGE 0 TO 15;
209
-    VARIABLE result : std_logic_vector(0 TO 3);
210
-  BEGIN
211
-    int := input_vector( 0 ) & input_vector( 5 );
212
-    i := to_integer( unsigned( int ) );
213
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
214
-    result := std_logic_vector( to_unsigned( s4_table( i, j ), 4 ) );
215
-    RETURN result;
216
-  END FUNCTION s4;
217
-
218
-  FUNCTION s5 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
219
-    VARIABLE int : std_logic_vector(0 TO 1);
220
-    VARIABLE i : integer RANGE 0 TO 3;
221
-    VARIABLE j : integer RANGE 0 TO 15;
222
-    VARIABLE result : std_logic_vector(0 TO 3);
223
-  BEGIN
224
-    int := input_vector( 0 ) & input_vector( 5 );
225
-    i := to_integer( unsigned( int ) );
226
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
227
-    result := std_logic_vector( to_unsigned( s5_table( i, j ), 4 ) );
228
-    RETURN result;
229
-  END FUNCTION s5;
230
-
231
-  FUNCTION s6 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
232
-    VARIABLE int : std_logic_vector(0 TO 1);
233
-    VARIABLE i : integer RANGE 0 TO 3;
234
-    VARIABLE j : integer RANGE 0 TO 15;
235
-    VARIABLE result : std_logic_vector(0 TO 3);
236
-  BEGIN
237
-    int := input_vector( 0 ) & input_vector( 5 );
238
-    i := to_integer( unsigned( int ) );
239
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
240
-    result := std_logic_vector( to_unsigned( s6_table( i, j ), 4 ) );
241
-    RETURN result;
242
-  END FUNCTION s6;
243
-
244
-  FUNCTION s7 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
245
-    VARIABLE int : std_logic_vector(0 TO 1);
246
-    VARIABLE i : integer RANGE 0 TO 3;
247
-    VARIABLE j : integer RANGE 0 TO 15;
248
-    VARIABLE result : std_logic_vector(0 TO 3);
249
-  BEGIN
250
-    int := input_vector( 0 ) & input_vector( 5 );
251
-    i := to_integer( unsigned( int ) );
252
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
253
-    result := std_logic_vector( to_unsigned( s7_table( i, j ), 4 ) );
254
-    RETURN result;
255
-  END FUNCTION s7;
256
-
257
-  FUNCTION s8 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
258
-    VARIABLE int : std_logic_vector(0 TO 1);
259
-    VARIABLE i : integer RANGE 0 TO 3;
260
-    VARIABLE j : integer RANGE 0 TO 15;
261
-    VARIABLE result : std_logic_vector(0 TO 3);
262
-  BEGIN
263
-    int := input_vector( 0 ) & input_vector( 5 );
264
-    i := to_integer( unsigned( int ) );
265
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
266
-    result := std_logic_vector( to_unsigned( s8_table( i, j ), 4 ) );
267
-    RETURN result;
268
-  END FUNCTION s8;
269
-
270
-  FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS
271
-    VARIABLE result : std_logic_vector(0 TO 31);
272
-  BEGIN
273
-    FOR index IN 0 TO 31 LOOP
274
-      result( index ) := input_vector( p_table( index ) );
275
-    END LOOP;
276
-    RETURN result;
277
-  END FUNCTION p;
278
-
279
-  FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector IS
280
-    VARIABLE intern : std_logic_vector(0 TO 47);
281
-    VARIABLE result : std_logic_vector(0 TO 31);
282
-  BEGIN
283
-    intern := e( input_r ) xor input_key;
284
-    result := p( s1( intern(0 TO 5) ) & s2( intern(6 TO 11) ) & s3( intern(12 TO 17) ) & s4( intern(18 TO 23) ) &
285
-              s5( intern(24 TO 29) ) & s6( intern(30 TO 35) ) & s7( intern(36 TO 41) ) & s8( intern(42 TO 47) ) );
286
-    RETURN result;
287
-  END FUNCTION f;
288
-
289
-  FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
290
-    VARIABLE result : std_logic_vector(0 TO 27);
291
-  BEGIN
292
-    FOR index IN 0 TO 27 LOOP
293
-      result( index ) := input_vector( pc1c_table( index ) );
294
-    END LOOP;
295
-    RETURN result;
296
-  END FUNCTION pc1_c;
297
-
298
-  FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
299
-
300
-    VARIABLE result : std_logic_vector(0 TO 27);
301
-  BEGIN
302
-    FOR index IN 0 TO 27 LOOP
303
-      result( index ) := input_vector( pc1d_table( index ) );
304
-    END LOOP;
305
-    RETURN result;
306
-  END FUNCTION pc1_d;
307
-
308
-  FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector IS
309
-    VARIABLE result : std_logic_vector(0 TO 47);
310
-  BEGIN
311
-    FOR index IN 0 TO 47 LOOP
312
-      result( index ) := input_vector( pc2_table( index ) );
313
-    END LOOP;
314
-    RETURN result;
315
-  END FUNCTION pc2;
316
-
317
-
318
-END PACKAGE BODY des_pkg;

+ 55
- 83
tdes/rtl/vhdl/tdes.vhd View File

@@ -19,29 +19,28 @@
19 19
 -- ======================================================================
20 20
 
21 21
 
22
-
23
-
24 22
 library ieee;
25 23
 use ieee.std_logic_1164.all;
26 24
 use ieee.numeric_std.all;
25
+
27 26
 use work.des_pkg.all;
28 27
 
29 28
 
29
+
30 30
 entity tdes is
31 31
   port (
32 32
     reset_i     : in  std_logic;                  -- async reset
33 33
     clk_i       : in  std_logic;                  -- clock
34 34
     mode_i      : in  std_logic;                  -- tdes-modus: 0 = encrypt, 1 = decrypt
35
-    key1_i      : in  std_logic_vector(0 TO 63);  -- key input
36
-    key2_i      : in  std_logic_vector(0 TO 63);  -- key input
37
-    key3_i      : in  std_logic_vector(0 TO 63);  -- key input
38
-    data_i      : in  std_logic_vector(0 TO 63);  -- data input
35
+    key1_i      : in  std_logic_vector(0 to 63);  -- key input
36
+    key2_i      : in  std_logic_vector(0 to 63);  -- key input
37
+    key3_i      : in  std_logic_vector(0 to 63);  -- key input
38
+    data_i      : in  std_logic_vector(0 to 63);  -- data input
39 39
     valid_i     : in  std_logic;                  -- input key/data valid flag
40
-    data_o      : out std_logic_vector(0 TO 63);  -- data output
40
+    accept_o    : out std_logic;
41
+    data_o      : out std_logic_vector(0 to 63);  -- data output
41 42
     valid_o     : out std_logic;                  -- output data valid flag
42
-    ready_o     : out std_logic
43
+    accept_i    : in  std_logic
43 44
   );
44 45
 end entity tdes;
45 46
 
@@ -49,56 +48,36 @@ end entity tdes;
49 48
 architecture rtl of tdes is
50 49
 
51 50
 
52
-  component des is
53
-    port (
54
-      reset_i     : in  std_logic;
55
-      clk_i       : IN  std_logic;                  -- clock
56
-      mode_i      : IN  std_logic;                  -- des-modus: 0 = encrypt, 1 = decrypt
57
-      key_i       : IN  std_logic_vector(0 TO 63);  -- key input
58
-      data_i      : IN  std_logic_vector(0 TO 63);  -- data input
59
-      valid_i     : IN  std_logic;                  -- input key/data valid flag
60
-      data_o      : OUT std_logic_vector(0 TO 63);  -- data output
61
-      valid_o     : OUT std_logic                   -- output data valid flag
62
-    );
63
-  end component des;
64
-
65
-
66
-  signal s_ready         : std_logic;
67
-  signal s_mode          : std_logic;
68
-  signal s_des2_mode     : std_logic;
69
-  signal s_des1_validin  : std_logic := '0';
70
-  signal s_des1_validout : std_logic;
71
-  signal s_des2_validout : std_logic;
72
-  signal s_des3_validout : std_logic;
73
-  signal s_key1          : std_logic_vector(0 to 63);
74
-  signal s_key2          : std_logic_vector(0 to 63);
75
-  signal s_key3          : std_logic_vector(0 to 63);
76
-  signal s_des1_key      : std_logic_vector(0 to 63);
77
-  signal s_des3_key      : std_logic_vector(0 to 63);
78
-  signal s_des1_dataout  : std_logic_vector(0 to 63);
79
-  signal s_des2_dataout  : std_logic_vector(0 to 63);
51
+  signal s_mode           : std_logic;
52
+  signal s_des1_validout  : std_logic;
53
+  signal s_des2_validout  : std_logic;
54
+  signal s_des2_acceptout : std_logic;
55
+  signal s_des3_acceptout : std_logic;
56
+  signal s_key1           : std_logic_vector(0 to 63);
57
+  signal s_key2           : std_logic_vector(0 to 63);
58
+  signal s_key3           : std_logic_vector(0 to 63);
59
+  signal s_des1_key       : std_logic_vector(0 to 63);
60
+  signal s_des3_key       : std_logic_vector(0 to 63);
61
+  signal s_des1_dataout   : std_logic_vector(0 to 63);
62
+  signal s_des2_dataout   : std_logic_vector(0 to 63);
80 63
 
81
-begin
82 64
 
65
+begin
83 66
 
84
-  ready_o        <= s_ready;
85
-  valid_o        <= s_des3_validout;
86
-  s_des2_mode    <= not(s_mode);
87
-  s_des1_validin <= valid_i and s_ready;
88 67
 
89 68
   s_des1_key <= key1_i when mode_i = '0' else key3_i;
90 69
   s_des3_key <= s_key3 when s_mode = '0' else s_key1;
91 70
 
92 71
 
93
-  inputregister : process(clk_i, reset_i) is
72
+  inputregister : process (clk_i, reset_i) is
94 73
   begin
95
-    if(reset_i = '0') then
74
+    if (reset_i = '0') then
96 75
       s_mode  <= '0';
97 76
       s_key1  <= (others => '0');
98 77
       s_key2  <= (others => '0');
99 78
       s_key3  <= (others => '0');
100 79
     elsif(rising_edge(clk_i)) then
101
-      if(valid_i = '1' and s_ready = '1') then
80
+      if (valid_i = '1' and accept_o = '1') then
102 81
         s_mode <= mode_i;
103 82
         s_key1 <= key1_i;
104 83
         s_key2 <= key2_i;
@@ -108,57 +87,48 @@ begin
108 87
   end process inputregister;
109 88
 
110 89
 
111
-  outputregister : process(clk_i, reset_i) is
112
-  begin
113
-    if(reset_i = '0') then
114
-      s_ready   <= '1';
115
-    elsif(rising_edge(clk_i)) then
116
-      if(valid_i = '1' and s_ready = '1') then
117
-        s_ready <= '0';
118
-      end if;
119
-      if(s_des3_validout = '1') then
120
-        s_ready   <= '1';
121
-      end if;
122
-    end if;
123
-  end process outputregister;
124
-
125
-
126 90
   i1_des : des
127 91
     port map (
128
-      reset_i => reset_i,
129
-      clk_i   => clk_i,
130
-      mode_i  => mode_i,
131
-      key_i   => s_des1_key,
132
-      data_i  => data_i,
133
-      valid_i => s_des1_validin,
134
-      data_o  => s_des1_dataout,
135
-      valid_o => s_des1_validout
92
+      reset_i  => reset_i,
93
+      clk_i    => clk_i,
94
+      mode_i   => mode_i,
95
+      key_i    => s_des1_key,
96
+      data_i   => data_i,
97
+      valid_i  => valid_i,
98
+      accept_o => accept_o,
99
+      data_o   => s_des1_dataout,
100
+      valid_o  => s_des1_validout,
101
+      accept_i => s_des2_acceptout
136 102
     );
137 103
 
138 104
 
139 105
   i2_des : des
140 106
     port map (
141
-      reset_i => reset_i,
142
-      clk_i   => clk_i,
143
-      mode_i  => s_des2_mode,
144
-      key_i   => s_key2,
145
-      data_i  => s_des1_dataout,
146
-      valid_i => s_des1_validout,
147
-      data_o  => s_des2_dataout,
148
-      valid_o => s_des2_validout
107
+      reset_i  => reset_i,
108
+      clk_i    => clk_i,
109
+      mode_i   => not s_mode,
110
+      key_i    => s_key2,
111
+      data_i   => s_des1_dataout,
112
+      valid_i  => s_des1_validout,
113
+      accept_o => s_des2_acceptout,
114
+      data_o   => s_des2_dataout,
115
+      valid_o  => s_des2_validout,
116
+      accept_i => s_des3_acceptout
149 117
     );
150 118
 
151 119
 
152 120
   i3_des : des
153 121
     port map (
154
-      reset_i => reset_i,
155
-      clk_i   => clk_i,
156
-      mode_i  => s_mode,
157
-      key_i   => s_des3_key,
158
-      data_i  => s_des2_dataout,
159
-      valid_i => s_des2_validout,
160
-      data_o  => data_o,
161
-      valid_o => s_des3_validout
122
+      reset_i  => reset_i,
123
+      clk_i    => clk_i,
124
+      mode_i   => s_mode,
125
+      key_i    => s_des3_key,
126
+      data_i   => s_des2_dataout,
127
+      valid_i  => s_des2_validout,
128
+      accept_o => s_des3_acceptout,
129
+      data_o   => data_o,
130
+      valid_o  => valid_o,
131
+      accept_i => accept_i
162 132
     );
163 133
 
164 134
 

tdes/sim/vhdl/makefile → tdes/sim/vhdl/Makefile View File

@@ -1,5 +1,5 @@
1 1
 # ======================================================================
2
-# DES encryption/decryption
2
+# TDES encryption/decryption
3 3
 # algorithm according to FIPS 46-3 specification
4 4
 # Copyright (C) 2011 Torsten Meissner
5 5
 #-----------------------------------------------------------------------
@@ -19,24 +19,30 @@
19 19
 # ======================================================================
20 20
 
21 21
 
22
-SRC_FILES = ../../rtl/vhdl/des_pkg.vhd ../../rtl/vhdl/des.vhd ../../rtl/vhdl/tdes.vhd
22
+DES_SRC_FILES  := ../../../des/rtl/vhdl/des_pkg.vhd ../../../des/rtl/vhdl/des.vhd
23
+TDES_SRC_FILES := ../../rtl/vhdl/tdes.vhd
24
+SRC_FILES      := $(DES_SRC_FILES) $(TDES_SRC_FILES)
25
+VHD_STD        := 08
23 26
 
24 27
 
25
-all : sim wave
26
-
28
+.PHONY: sim
27 29
 sim : tb_tdes.ghw
28 30
 
29
-tb_tdes.ghw : $(SRC_FILES) tb_tdes.vhd
30
-	ghdl -a $(SRC_FILES) tb_tdes.vhd
31
-	ghdl -e tb_tdes
31
+.PHONY: all
32
+all : wave
33
+
34
+
35
+tb_des.o: $(SRC_FILES) tb_tdes.vhd
36
+	ghdl -a --std=$(VHD_STD) $(SRC_FILES) tb_tdes.vhd
37
+
38
+tb_tdes.ghw : tb_des.o
39
+	ghdl -e --std=$(VHD_STD) tb_tdes
32 40
 	ghdl -r tb_tdes --wave=tb_tdes.ghw --assert-level=error --stop-time=45us
33
-	
41
+
34 42
 wave : tb_tdes.ghw
35 43
 	gtkwave -s tb_tdes.tcl tb_tdes.ghw
36
-	
44
+
45
+
37 46
 clean :
38
-	echo "# cleaning simulation files"
39
-	rm -f *.ghw
40
-	rm -f *.o
41
-	rm -f tb_tdes
42
-	rm -f work*.cf
47
+	echo "# Cleaning files"
48
+	rm -f *.ghw *.o tb_tdes work*.cf

+ 26
- 40
tdes/sim/vhdl/tb_tdes.vhd View File

@@ -19,15 +19,12 @@
19 19
 -- ======================================================================
20 20
 
21 21
 
22
-
23
-
24 22
 library ieee;
25 23
 use ieee.std_logic_1164.all;
26 24
 use ieee.numeric_std.all;
27 25
 
28 26
 
27
+
29 28
 entity tb_tdes is
30 29
 end entity tb_tdes;
31 30
 
@@ -56,26 +53,11 @@ architecture rtl of tb_tdes is
56 53
   signal s_key3     : std_logic_vector(0 to 63) := (others => '0');
57 54
   signal s_datain   : std_logic_vector(0 to 63) := (others => '0');
58 55
   signal s_validin  : std_logic := '0';
59
-  signal s_ready    : std_logic := '0';
60
-  signal s_dataout  : std_logic_vector(0 to 63);
61
-  signal s_validout : std_logic := '0';
62
-
63
-
64
-  component tdes is
65
-    port (
66
-      reset_i     : in  std_logic;
67
-      clk_i       : in  std_logic;
68
-      mode_i      : in  std_logic;
69
-      key1_i      : in  std_logic_vector(0 to 63);
70
-      key2_i      : in  std_logic_vector(0 TO 63);
71
-      key3_i      : in  std_logic_vector(0 TO 63);
72
-      data_i      : in  std_logic_vector(0 TO 63);
73
-      valid_i     : in  std_logic;
74
-      data_o      : out std_logic_vector(0 TO 63);
75
-      valid_o     : out std_logic;
76
-      ready_o     : out std_logic
77
-    );
78
-  end component tdes;
56
+  signal s_acceptin : std_logic;
57
+
58
+  signal s_dataout   : std_logic_vector(0 to 63);
59
+  signal s_validout  : std_logic := '0';
60
+  signal s_acceptout : std_logic := '0';
79 61
 
80 62
 
81 63
 begin
@@ -87,23 +69,23 @@ begin
87 69
 
88 70
   teststimuliP : process is
89 71
   begin
90
-    s_mode    <= '0';
91
-    s_validin <= '0';
92
-    s_key1    <= (others => '0');
93
-    s_key2    <= (others => '0');
94
-    s_key3    <= (others => '0');
95
-    s_datain  <= (others => '0');
72
+    s_mode      <= '0';
73
+    s_validin   <= '0';
74
+    s_key1      <= (others => '0');
75
+    s_key2      <= (others => '0');
76
+    s_key3      <= (others => '0');
77
+    s_datain    <= (others => '0');
96 78
     wait until s_reset = '1';
97 79
     -- ENCRYPTION TESTS
98 80
     -- cbc known answers test
99 81
     for index in c_table_test_plain'range loop
100
-      wait until rising_edge(s_clk) and s_ready = '1';
82
+      wait until rising_edge(s_clk);
101 83
         s_key1    <= x"1111111111111111";
102 84
         s_key2    <= x"5555555555555555";
103 85
         s_key3    <= x"9999999999999999";
104 86
         s_validin <= '1';
105 87
         s_datain  <= c_table_test_plain(index);
106
-      wait until rising_edge(s_clk);
88
+      wait until s_acceptin = '1' and rising_edge(s_clk);
107 89
         s_validin <= '0';
108 90
     end loop;
109 91
     wait until rising_edge(s_clk);
@@ -117,30 +99,31 @@ begin
117 99
     -- DECRYPTION TESTS
118 100
     -- cbc known answer test
119 101
     for index in c_table_test_plain'range loop
120
-      wait until rising_edge(s_clk) and s_ready = '1';
102
+      wait until rising_edge(s_clk);
121 103
         s_key1    <= x"1111111111111111";
122 104
         s_key2    <= x"5555555555555555";
123 105
         s_key3    <= x"9999999999999999";
124 106
         s_mode    <= '1';
125 107
         s_validin <= '1';
126 108
         s_datain  <= s_tdes_answers(index);
127
-      wait until rising_edge(s_clk);
109
+      wait until s_acceptin = '1' and rising_edge(s_clk);
128 110
         s_validin <= '0';
129 111
         s_mode    <= '0';
130 112
     end loop;
131 113
     wait until rising_edge(s_clk);
132
-    s_mode    <= '0';
133
-    s_validin <= '0';
134
-    s_key1    <= (others => '0');
135
-    s_key2    <= (others => '0');
136
-    s_key3    <= (others => '0');
137
-    s_datain  <= (others => '0');
114
+    s_mode      <= '0';
115
+    s_validin   <= '0';
116
+    s_key1      <= (others => '0');
117
+    s_key2      <= (others => '0');
118
+    s_key3      <= (others => '0');
119
+    s_datain    <= (others => '0');
138 120
     wait;
139 121
   end process teststimuliP;
140 122
 
141 123
 
142 124
   testcheckerP : process is
143 125
   begin
126
+    s_acceptout <= '1';
144 127
     report "# ENCRYPTION TESTS";
145 128
     for index in c_table_test_plain'range loop
146 129
       wait until rising_edge(s_clk) and s_validout = '1';
@@ -159,7 +142,7 @@ begin
159 142
   end process testcheckerP;
160 143
 
161 144
 
162
-  i_tdes : tdes
145
+  i_tdes : entity work.tdes
163 146
   port map (
164 147
     reset_i  => s_reset,
165 148
     clk_i    => s_clk,
@@ -169,9 +152,10 @@ begin
169 152
     key3_i   => s_key3,
170 153
     data_i   => s_datain,
171 154
     valid_i  => s_validin,
155
+    accept_o => s_acceptin,
172 156
     data_o   => s_dataout,
173 157
     valid_o  => s_validout,
174
-    ready_o  => s_ready
158
+    accept_i => s_acceptout
175 159
   );
176 160
 
177 161
 

+ 13
- 12
tdes/syn/vhdl/Makefile View File

@@ -19,29 +19,30 @@
19 19
 # ======================================================================
20 20
 
21 21
 
22
-DES_SRC_FILES  := ../../../des/rtl/vhdl/des_pkg.vhd ../../../des/rtl/vhdl/des.vhd
23
-TDES_SRC_FILES := ../../rtl/vhdl/tdes.vhd
24
-SRC_FILES      := $(DES_SRC_FILES) $(TDES_SRC_FILES)
25
-VHD_STD        := 08
22
+DESIGN_NAME      := tdes
23
+DES_SRC_FILES    := ../../../des/rtl/vhdl/des_pkg.vhd ../../../des/rtl/vhdl/des.vhd
24
+DESIGN_SRC_FILES := ../../rtl/vhdl/$(DESIGN_NAME).vhd
25
+SRC_FILES        := $(DES_SRC_FILES) $(DESIGN_SRC_FILES)
26
+VHD_STD          := 08
26 27
 
27 28
 
28 29
 .PHONY: all
29
-all : tdes_synth.vhd syn
30
+all : $(DESIGN_NAME)_synth.vhd syn
30 31
 
31 32
 .PHONY: syn
32
-syn: tdes.json
33
+syn: $(DESIGN_NAME).json
33 34
 
34 35
 
35
-tdes.o: $(SRC_FILES)
36
+$(DESIGN_NAME).o: $(SRC_FILES)
36 37
 	ghdl -a --std=$(VHD_STD) $(SRC_FILES)
37 38
 
38
-tdes_synth.vhd: $(SRC_FILES)
39
-	ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e tdes > $@
39
+$(DESIGN_NAME)_synth.vhd: $(SRC_FILES)
40
+	ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@
40 41
 
41
-tdes.json: tdes.o
42
-	yosys -m ghdl -p 'ghdl --std=08 --no-formal tdes; synth_ice40 -json $@'
42
+$(DESIGN_NAME).json: $(DESIGN_NAME).o
43
+	yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@'
43 44
 
44 45
 
45 46
 clean :
46 47
 	echo "# Cleaning files"
47
-	rm -f *.o work*.cf tdes.json tdes_synth.vhd
48
+	rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd