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Update CI-badge; add hint to VHPIdirect use in *aes testbenches

T. Meissner 1 month ago
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      README.md

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-<p align="center">
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-  <a title="GitHub Actions workflow 'simulation'" href="https://github.com/tmeissner/cryptocores/actions?query=workflow%3ASimulation"><img alt="'simulation' workflow Status" src="https://img.shields.io/github/workflow/status/tmeissner/cryptocores/Simulation/master?longCache=true&style=flat-square&label=build&logo=Github%20Actions&logoColor=fff"></a><!--
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-</p>
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+[![simulation](https://img.shields.io/github/workflow/status/tmeissner/cryptocores/Simulation/master?longCache=true&style=flat-square&label=simulation&logo=Github%20Actions&logoColor=fff)](https://github.com/tmeissner/cryptocores/actions?query=workflow%3ASimulation)
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 # cryptocores
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 Cryptography IP-cores & tests written in VHDL / Verilog
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 only (local) variables instead of (global) signals. Furthermore they were used
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 how to do a VHDL-to-Verilog conversion for learning purposes.
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+The testbenches to verify [AES](aes/sim/vhdl/) and [CTR-AES](ctraes/sim/vhdl/) are examples
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+how useful GHDLs VHPIdirect is. They use openSSL as reference models to check the correctness
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+of the VHDL implementation.
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 *HINT:*
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 The tests of some algorithms use the OSVVM library, which is redistributed as