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integrate s1-s8() into one s() function with additional parameter s_table; convert lower to upper case

T. Meissner 5 years ago
parent
commit
8a9b30940e
2 changed files with 324 additions and 416 deletions
  1. 215
    217
      des/rtl/vhdl/des.vhd
  2. 109
    199
      des/rtl/vhdl/des_pkg.vhd

+ 215
- 217
des/rtl/vhdl/des.vhd View File

@@ -32,15 +32,15 @@ entity des is
32 32
   );
33 33
   port (
34 34
     reset_i     : in  std_logic;                  -- async reset
35
-    clk_i       : IN  std_logic;                  -- clock
36
-    mode_i      : IN  std_logic;                  -- des-modus: 0 = encrypt, 1 = decrypt
37
-    key_i       : IN  std_logic_vector(0 TO 63);  -- key input
38
-    data_i      : IN  std_logic_vector(0 TO 63);  -- data input
39
-    valid_i     : IN  std_logic;                  -- input key/data valid
40
-    accept_o    : out std_logic;                  -- input data accepted
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-    data_o      : OUT std_logic_vector(0 TO 63);  -- data output
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-    valid_o     : OUT std_logic;                  -- output data valid flag
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-    accept_i    : in  std_logic
35
+    clk_i       : in  std_logic;                  -- clock
36
+    mode_i      : in  std_logic;                  -- des-modus: 0 = encrypt, 1 = decrypt
37
+    key_i       : in  std_logic_vector(0 to 63);  -- key input
38
+    data_i      : in  std_logic_vector(0 to 63);  -- data input
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+    valid_i     : in  std_logic;                  -- input key/data valid
40
+    accept_o    : out std_logic;                  -- input accept
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+    data_o      : out std_logic_vector(0 to 63);  -- data output
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+    valid_o     : out std_logic;                  -- output data valid flag
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+    accept_i    : in  std_logic                   -- output accept
44 44
   );
45 45
 end entity des;
46 46
 
@@ -56,294 +56,294 @@ begin
56 56
 
57 57
   begin
58 58
 
59
-    crypt : PROCESS (clk_i, reset_i) IS
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+    crypt : process (clk_i, reset_i) is
60 60
       -- variables for key calculation
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-      VARIABLE c0  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c1  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c2  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c3  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c4  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c5  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c6  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c7  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c8  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c9  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c10 : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c11 : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c12 : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c13 : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c14 : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c15 : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE c16 : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d0  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d1  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d2  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d3  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d4  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d5  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d6  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d7  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d8  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d9  : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d10 : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d11 : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d12 : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d13 : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d14 : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d15 : std_logic_vector(0 TO 27) := (others => '0');
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-      VARIABLE d16 : std_logic_vector(0 TO 27) := (others => '0');
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+      variable c0  : std_logic_vector(0 to 27) := (others => '0');
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+      variable c1  : std_logic_vector(0 to 27) := (others => '0');
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+      variable c2  : std_logic_vector(0 to 27) := (others => '0');
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+      variable c3  : std_logic_vector(0 to 27) := (others => '0');
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+      variable c4  : std_logic_vector(0 to 27) := (others => '0');
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+      variable c5  : std_logic_vector(0 to 27) := (others => '0');
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+      variable c6  : std_logic_vector(0 to 27) := (others => '0');
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+      variable c7  : std_logic_vector(0 to 27) := (others => '0');
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+      variable c8  : std_logic_vector(0 to 27) := (others => '0');
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+      variable c9  : std_logic_vector(0 to 27) := (others => '0');
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+      variable c10 : std_logic_vector(0 to 27) := (others => '0');
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+      variable c11 : std_logic_vector(0 to 27) := (others => '0');
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+      variable c12 : std_logic_vector(0 to 27) := (others => '0');
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+      variable c13 : std_logic_vector(0 to 27) := (others => '0');
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+      variable c14 : std_logic_vector(0 to 27) := (others => '0');
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+      variable c15 : std_logic_vector(0 to 27) := (others => '0');
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+      variable c16 : std_logic_vector(0 to 27) := (others => '0');
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+      variable d0  : std_logic_vector(0 to 27) := (others => '0');
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+      variable d1  : std_logic_vector(0 to 27) := (others => '0');
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+      variable d2  : std_logic_vector(0 to 27) := (others => '0');
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+      variable d3  : std_logic_vector(0 to 27) := (others => '0');
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+      variable d4  : std_logic_vector(0 to 27) := (others => '0');
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+      variable d5  : std_logic_vector(0 to 27) := (others => '0');
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+      variable d6  : std_logic_vector(0 to 27) := (others => '0');
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+      variable d7  : std_logic_vector(0 to 27) := (others => '0');
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+      variable d8  : std_logic_vector(0 to 27) := (others => '0');
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+      variable d9  : std_logic_vector(0 to 27) := (others => '0');
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+      variable d10 : std_logic_vector(0 to 27) := (others => '0');
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+      variable d11 : std_logic_vector(0 to 27) := (others => '0');
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+      variable d12 : std_logic_vector(0 to 27) := (others => '0');
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+      variable d13 : std_logic_vector(0 to 27) := (others => '0');
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+      variable d14 : std_logic_vector(0 to 27) := (others => '0');
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+      variable d15 : std_logic_vector(0 to 27) := (others => '0');
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+      variable d16 : std_logic_vector(0 to 27) := (others => '0');
95 95
       -- key variables
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-      VARIABLE key1  : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key2  : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key3  : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key4  : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key5  : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key6  : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key7  : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key8  : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key9  : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key10 : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key11 : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key12 : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key13 : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key14 : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key15 : std_logic_vector(0 TO 47) := (others => '0');
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-      VARIABLE key16 : std_logic_vector(0 TO 47) := (others => '0');
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+      variable key1  : std_logic_vector(0 to 47) := (others => '0');
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+      variable key2  : std_logic_vector(0 to 47) := (others => '0');
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+      variable key3  : std_logic_vector(0 to 47) := (others => '0');
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+      variable key4  : std_logic_vector(0 to 47) := (others => '0');
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+      variable key5  : std_logic_vector(0 to 47) := (others => '0');
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+      variable key6  : std_logic_vector(0 to 47) := (others => '0');
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+      variable key7  : std_logic_vector(0 to 47) := (others => '0');
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+      variable key8  : std_logic_vector(0 to 47) := (others => '0');
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+      variable key9  : std_logic_vector(0 to 47) := (others => '0');
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+      variable key10 : std_logic_vector(0 to 47) := (others => '0');
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+      variable key11 : std_logic_vector(0 to 47) := (others => '0');
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+      variable key12 : std_logic_vector(0 to 47) := (others => '0');
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+      variable key13 : std_logic_vector(0 to 47) := (others => '0');
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+      variable key14 : std_logic_vector(0 to 47) := (others => '0');
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+      variable key15 : std_logic_vector(0 to 47) := (others => '0');
111
+      variable key16 : std_logic_vector(0 to 47) := (others => '0');
112 112
       -- variables for left & right data blocks
113
-      VARIABLE l0  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l1  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l2  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l3  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l4  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l5  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l6  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l7  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l8  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l9  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l10 : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l11 : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l12 : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l13 : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l14 : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l15 : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE l16 : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r0  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r1  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r2  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r3  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r4  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r5  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r6  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r7  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r8  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r9  : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r10 : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r11 : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r12 : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r13 : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r14 : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r15 : std_logic_vector( 0 TO 31) := (others => '0');
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-      VARIABLE r16 : std_logic_vector( 0 TO 31) := (others => '0');
113
+      variable l0  : std_logic_vector( 0 to 31) := (others => '0');
114
+      variable l1  : std_logic_vector( 0 to 31) := (others => '0');
115
+      variable l2  : std_logic_vector( 0 to 31) := (others => '0');
116
+      variable l3  : std_logic_vector( 0 to 31) := (others => '0');
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+      variable l4  : std_logic_vector( 0 to 31) := (others => '0');
118
+      variable l5  : std_logic_vector( 0 to 31) := (others => '0');
119
+      variable l6  : std_logic_vector( 0 to 31) := (others => '0');
120
+      variable l7  : std_logic_vector( 0 to 31) := (others => '0');
121
+      variable l8  : std_logic_vector( 0 to 31) := (others => '0');
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+      variable l9  : std_logic_vector( 0 to 31) := (others => '0');
123
+      variable l10 : std_logic_vector( 0 to 31) := (others => '0');
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+      variable l11 : std_logic_vector( 0 to 31) := (others => '0');
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+      variable l12 : std_logic_vector( 0 to 31) := (others => '0');
126
+      variable l13 : std_logic_vector( 0 to 31) := (others => '0');
127
+      variable l14 : std_logic_vector( 0 to 31) := (others => '0');
128
+      variable l15 : std_logic_vector( 0 to 31) := (others => '0');
129
+      variable l16 : std_logic_vector( 0 to 31) := (others => '0');
130
+      variable r0  : std_logic_vector( 0 to 31) := (others => '0');
131
+      variable r1  : std_logic_vector( 0 to 31) := (others => '0');
132
+      variable r2  : std_logic_vector( 0 to 31) := (others => '0');
133
+      variable r3  : std_logic_vector( 0 to 31) := (others => '0');
134
+      variable r4  : std_logic_vector( 0 to 31) := (others => '0');
135
+      variable r5  : std_logic_vector( 0 to 31) := (others => '0');
136
+      variable r6  : std_logic_vector( 0 to 31) := (others => '0');
137
+      variable r7  : std_logic_vector( 0 to 31) := (others => '0');
138
+      variable r8  : std_logic_vector( 0 to 31) := (others => '0');
139
+      variable r9  : std_logic_vector( 0 to 31) := (others => '0');
140
+      variable r10 : std_logic_vector( 0 to 31) := (others => '0');
141
+      variable r11 : std_logic_vector( 0 to 31) := (others => '0');
142
+      variable r12 : std_logic_vector( 0 to 31) := (others => '0');
143
+      variable r13 : std_logic_vector( 0 to 31) := (others => '0');
144
+      variable r14 : std_logic_vector( 0 to 31) := (others => '0');
145
+      variable r15 : std_logic_vector( 0 to 31) := (others => '0');
146
+      variable r16 : std_logic_vector( 0 to 31) := (others => '0');
147 147
       -- variables for mode & valid shift registers
148
-      VARIABLE mode  : std_logic_vector(0 TO 16) := (others => '0');
149
-      VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0');
150
-    BEGIN
148
+      variable mode  : std_logic_vector(0 to 16) := (others => '0');
149
+      variable valid : std_logic_vector(0 to 17) := (others => '0');
150
+    begin
151 151
       if(reset_i = '0') then
152 152
         data_o  <= (others => '0');
153 153
         valid_o <= '0';
154
-      elsif rising_edge( clk_i ) THEN
154
+      elsif rising_edge( clk_i ) then
155 155
         -- shift registers
156
-        valid(1 TO 17) := valid(0 TO 16);
156
+        valid(1 to 17) := valid(0 to 16);
157 157
         valid(0) := valid_i;
158
-        mode(1 TO 16) := mode(0 TO 15);
158
+        mode(1 to 16) := mode(0 to 15);
159 159
         mode(0)  := mode_i;
160 160
         -- output stage
161 161
         accept_o <= '1';
162 162
         valid_o  <= valid(17);
163 163
         data_o   <= ipn( ( r16 & l16 ) );
164 164
         -- 16. stage
165
-        IF mode(16) = '0' THEN
166
-          c16 := c15(1 TO 27) & c15(0);
167
-          d16 := d15(1 TO 27) & d15(0);
168
-        ELSE
169
-          c16 := c15(27) & c15(0 TO 26);
170
-          d16 := d15(27) & d15(0 TO 26);
171
-        END IF;
165
+        if mode(16) = '0' then
166
+          c16 := c15(1 to 27) & c15(0);
167
+          d16 := d15(1 to 27) & d15(0);
168
+        else
169
+          c16 := c15(27) & c15(0 to 26);
170
+          d16 := d15(27) & d15(0 to 26);
171
+        end if;
172 172
         key16 := pc2( ( c16 & d16 ) );
173 173
         l16 := r15;
174 174
         r16 := l15 xor ( f( r15, key16 ) );
175 175
         -- 15. stage
176
-        IF mode(15) = '0' THEN
177
-          c15 := c14(2 TO 27) & c14(0 TO 1);
178
-          d15 := d14(2 TO 27) & d14(0 TO 1);
179
-        ELSE
180
-          c15 := c14(26 TO 27) & c14(0 TO 25);
181
-          d15 := d14(26 TO 27) & d14(0 TO 25);
182
-        END IF;
176
+        if mode(15) = '0' then
177
+          c15 := c14(2 to 27) & c14(0 to 1);
178
+          d15 := d14(2 to 27) & d14(0 to 1);
179
+        else
180
+          c15 := c14(26 to 27) & c14(0 to 25);
181
+          d15 := d14(26 to 27) & d14(0 to 25);
182
+        end if;
183 183
         key15 := pc2( ( c15 & d15 ) );
184 184
         l15 := r14;
185 185
         r15 := l14 xor ( f( r14, key15 ) );
186 186
         -- 14. stage
187
-        IF mode(14) = '0' THEN
188
-          c14 := c13(2 TO 27) & c13(0 TO 1);
189
-          d14 := d13(2 TO 27) & d13(0 TO 1);
190
-        ELSE
191
-          c14 := c13(26 TO 27) & c13(0 TO 25);
192
-          d14 := d13(26 TO 27) & d13(0 TO 25);
193
-        END IF;
187
+        if mode(14) = '0' then
188
+          c14 := c13(2 to 27) & c13(0 to 1);
189
+          d14 := d13(2 to 27) & d13(0 to 1);
190
+        else
191
+          c14 := c13(26 to 27) & c13(0 to 25);
192
+          d14 := d13(26 to 27) & d13(0 to 25);
193
+        end if;
194 194
         key14 := pc2( ( c14 & d14 ) );
195 195
         l14 := r13;
196 196
         r14 := l13 xor ( f( r13, key14 ) );
197 197
         -- 13. stage
198
-        IF mode(13) = '0' THEN
199
-          c13 := c12(2 TO 27) & c12(0 TO 1);
200
-          d13 := d12(2 TO 27) & d12(0 TO 1);
201
-        ELSE
202
-          c13 := c12(26 TO 27) & c12(0 TO 25);
203
-          d13 := d12(26 TO 27) & d12(0 TO 25);
204
-        END IF;
198
+        if mode(13) = '0' then
199
+          c13 := c12(2 to 27) & c12(0 to 1);
200
+          d13 := d12(2 to 27) & d12(0 to 1);
201
+        else
202
+          c13 := c12(26 to 27) & c12(0 to 25);
203
+          d13 := d12(26 to 27) & d12(0 to 25);
204
+        end if;
205 205
         key13 := pc2( ( c13 & d13 ) );
206 206
         l13 := r12;
207 207
         r13 := l12 xor ( f( r12, key13 ) );
208 208
         -- 12. stage
209
-        IF mode(12) = '0' THEN
210
-          c12 := c11(2 TO 27) & c11(0 TO 1);
211
-          d12 := d11(2 TO 27) & d11(0 TO 1);
212
-        ELSE
213
-          c12 := c11(26 TO 27) & c11(0 TO 25);
214
-          d12 := d11(26 TO 27) & d11(0 TO 25);
215
-        END IF;
209
+        if mode(12) = '0' then
210
+          c12 := c11(2 to 27) & c11(0 to 1);
211
+          d12 := d11(2 to 27) & d11(0 to 1);
212
+        else
213
+          c12 := c11(26 to 27) & c11(0 to 25);
214
+          d12 := d11(26 to 27) & d11(0 to 25);
215
+        end if;
216 216
         key12 := pc2( ( c12 & d12 ) );
217 217
         l12 := r11;
218 218
         r12 := l11 xor ( f( r11, key12 ) );
219 219
         -- 11. stage
220
-        IF mode(11) = '0' THEN
221
-          c11 := c10(2 TO 27) & c10(0 TO 1);
222
-          d11 := d10(2 TO 27) & d10(0 TO 1);
223
-        ELSE
224
-          c11 := c10(26 TO 27) & c10(0 TO 25);
225
-          d11 := d10(26 TO 27) & d10(0 TO 25);
226
-        END IF;
220
+        if mode(11) = '0' then
221
+          c11 := c10(2 to 27) & c10(0 to 1);
222
+          d11 := d10(2 to 27) & d10(0 to 1);
223
+        else
224
+          c11 := c10(26 to 27) & c10(0 to 25);
225
+          d11 := d10(26 to 27) & d10(0 to 25);
226
+        end if;
227 227
         key11 := pc2( ( c11 & d11 ) );
228 228
         l11 := r10;
229 229
         r11 := l10 xor ( f( r10, key11 ) );
230 230
         -- 10. stage
231
-        IF mode(10) = '0' THEN
232
-          c10 := c9(2 TO 27) & c9(0 TO 1);
233
-          d10 := d9(2 TO 27) & d9(0 TO 1);
234
-        ELSE
235
-          c10 := c9(26 TO 27) & c9(0 TO 25);
236
-          d10 := d9(26 TO 27) & d9(0 TO 25);
237
-        END IF;
231
+        if mode(10) = '0' then
232
+          c10 := c9(2 to 27) & c9(0 to 1);
233
+          d10 := d9(2 to 27) & d9(0 to 1);
234
+        else
235
+          c10 := c9(26 to 27) & c9(0 to 25);
236
+          d10 := d9(26 to 27) & d9(0 to 25);
237
+        end if;
238 238
         key10 := pc2( ( c10 & d10 ) );
239 239
         l10 := r9;
240 240
         r10 := l9 xor ( f( r9, key10 ) );
241 241
         -- 9. stage
242
-        IF mode(9) = '0' THEN
243
-          c9 := c8(1 TO 27) & c8(0);
244
-          d9 := d8(1 TO 27) & d8(0);
245
-        ELSE
246
-          c9 := c8(27) & c8(0 TO 26);
247
-          d9 := d8(27) & d8(0 TO 26);
248
-        END IF;
242
+        if mode(9) = '0' then
243
+          c9 := c8(1 to 27) & c8(0);
244
+          d9 := d8(1 to 27) & d8(0);
245
+        else
246
+          c9 := c8(27) & c8(0 to 26);
247
+          d9 := d8(27) & d8(0 to 26);
248
+        end if;
249 249
         key9 := pc2( ( c9 & d9 ) );
250 250
         l9 := r8;
251 251
         r9 := l8 xor ( f( r8, key9 ) );
252 252
         -- 8. stage
253
-        IF mode(8) = '0' THEN
254
-          c8 := c7(2 TO 27) & c7(0 TO 1);
255
-          d8 := d7(2 TO 27) & d7(0 TO 1);
256
-        ELSE
257
-          c8 := c7(26 TO 27) & c7(0 TO 25);
258
-          d8 := d7(26 TO 27) & d7(0 TO 25);
259
-        END IF;
253
+        if mode(8) = '0' then
254
+          c8 := c7(2 to 27) & c7(0 to 1);
255
+          d8 := d7(2 to 27) & d7(0 to 1);
256
+        else
257
+          c8 := c7(26 to 27) & c7(0 to 25);
258
+          d8 := d7(26 to 27) & d7(0 to 25);
259
+        end if;
260 260
         key8 := pc2( ( c8 & d8 ) );
261 261
         l8 := r7;
262 262
         r8 := l7 xor ( f( r7, key8 ) );
263 263
         -- 7. stage
264
-        IF mode(7) = '0' THEN
265
-          c7 := c6(2 TO 27) & c6(0 TO 1);
266
-          d7 := d6(2 TO 27) & d6(0 TO 1);
267
-        ELSE
268
-          c7 := c6(26 TO 27) & c6(0 TO 25);
269
-          d7 := d6(26 TO 27) & d6(0 TO 25);
270
-        END IF;
264
+        if mode(7) = '0' then
265
+          c7 := c6(2 to 27) & c6(0 to 1);
266
+          d7 := d6(2 to 27) & d6(0 to 1);
267
+        else
268
+          c7 := c6(26 to 27) & c6(0 to 25);
269
+          d7 := d6(26 to 27) & d6(0 to 25);
270
+        end if;
271 271
         key7 := pc2( ( c7 & d7 ) );
272 272
         l7 := r6;
273 273
         r7 := l6 xor ( f( r6, key7 ) );
274 274
         -- 6. stage
275
-        IF mode(6) = '0' THEN
276
-          c6 := c5(2 TO 27) & c5(0 TO 1);
277
-          d6 := d5(2 TO 27) & d5(0 TO 1);
278
-        ELSE
279
-          c6 := c5(26 TO 27) & c5(0 TO 25);
280
-          d6 := d5(26 TO 27) & d5(0 TO 25);
281
-        END IF;
275
+        if mode(6) = '0' then
276
+          c6 := c5(2 to 27) & c5(0 to 1);
277
+          d6 := d5(2 to 27) & d5(0 to 1);
278
+        else
279
+          c6 := c5(26 to 27) & c5(0 to 25);
280
+          d6 := d5(26 to 27) & d5(0 to 25);
281
+        end if;
282 282
         key6 := pc2( ( c6 & d6 ) );
283 283
         l6 := r5;
284 284
         r6 := l5 xor ( f( r5, key6 ) );
285 285
         -- 5. stage
286
-        IF mode(5) = '0' THEN
287
-          c5 := c4(2 TO 27) & c4(0 TO 1);
288
-          d5 := d4(2 TO 27) & d4(0 TO 1);
289
-        ELSE
290
-          c5 := c4(26 TO 27) & c4(0 TO 25);
291
-          d5 := d4(26 TO 27) & d4(0 TO 25);
292
-        END IF;
286
+        if mode(5) = '0' then
287
+          c5 := c4(2 to 27) & c4(0 to 1);
288
+          d5 := d4(2 to 27) & d4(0 to 1);
289
+        else
290
+          c5 := c4(26 to 27) & c4(0 to 25);
291
+          d5 := d4(26 to 27) & d4(0 to 25);
292
+        end if;
293 293
         key5 := pc2( ( c5 & d5 ) );
294 294
         l5 := r4;
295 295
         r5 := l4 xor ( f( r4, key5 ) );
296 296
         -- 4. stage
297
-        IF mode(4) = '0' THEN
298
-          c4 := c3(2 TO 27) & c3(0 TO 1);
299
-          d4 := d3(2 TO 27) & d3(0 TO 1);
300
-        ELSE
301
-          c4 := c3(26 TO 27) & c3(0 TO 25);
302
-          d4 := d3(26 TO 27) & d3(0 TO 25);
303
-        END IF;
297
+        if mode(4) = '0' then
298
+          c4 := c3(2 to 27) & c3(0 to 1);
299
+          d4 := d3(2 to 27) & d3(0 to 1);
300
+        else
301
+          c4 := c3(26 to 27) & c3(0 to 25);
302
+          d4 := d3(26 to 27) & d3(0 to 25);
303
+        end if;
304 304
         key4 := pc2( ( c4 & d4 ) );
305 305
         l4 := r3;
306 306
         r4 := l3 xor ( f( r3, key4 ) );
307 307
         -- 3. stage
308
-        IF mode(3) = '0' THEN
309
-          c3 := c2(2 TO 27) & c2(0 TO 1);
310
-          d3 := d2(2 TO 27) & d2(0 TO 1);
311
-        ELSE
312
-          c3 := c2(26 TO 27) & c2(0 TO 25);
313
-          d3 := d2(26 TO 27) & d2(0 TO 25);
314
-        END IF;
308
+        if mode(3) = '0' then
309
+          c3 := c2(2 to 27) & c2(0 to 1);
310
+          d3 := d2(2 to 27) & d2(0 to 1);
311
+        else
312
+          c3 := c2(26 to 27) & c2(0 to 25);
313
+          d3 := d2(26 to 27) & d2(0 to 25);
314
+        end if;
315 315
         key3 := pc2( ( c3 & d3 ) );
316 316
         l3 := r2;
317 317
         r3 := l2 xor ( f( r2, key3 ) );
318 318
         -- 2. stage
319
-        IF mode(2) = '0' THEN
320
-          c2 := c1(1 TO 27) & c1(0);
321
-          d2 := d1(1 TO 27) & d1(0);
322
-        ELSE
323
-          c2 := c1(27) & c1(0 TO 26);
324
-          d2 := d1(27) & d1(0 TO 26);
325
-        END IF;
319
+        if mode(2) = '0' then
320
+          c2 := c1(1 to 27) & c1(0);
321
+          d2 := d1(1 to 27) & d1(0);
322
+        else
323
+          c2 := c1(27) & c1(0 to 26);
324
+          d2 := d1(27) & d1(0 to 26);
325
+        end if;
326 326
         key2 := pc2( ( c2 & d2 ) );
327 327
         l2 := r1;
328 328
         r2 := l1 xor ( f( r1, key2 ) );
329 329
         -- 1. stage
330
-        IF mode(1) = '0' THEN
331
-          c1 := c0(1 TO 27) & c0(0);
332
-          d1 := d0(1 TO 27) & d0(0);
333
-        ELSE
330
+        if mode(1) = '0' then
331
+          c1 := c0(1 to 27) & c0(0);
332
+          d1 := d0(1 to 27) & d0(0);
333
+        else
334 334
           c1 := c0;
335 335
           d1 := d0;
336
-        END IF;
336
+        end if;
337 337
         key1 := pc2( ( c1 & d1 ) );
338 338
         l1 := r0;
339 339
         r1 := l0 xor ( f( r0, key1 ) );
340 340
         -- input stage
341
-        l0 := ip( data_i )(0 TO 31);
342
-        r0 := ip( data_i )(32 TO 63);
341
+        l0 := ip( data_i )(0 to 31);
342
+        r0 := ip( data_i )(32 to 63);
343 343
         c0 := pc1_c( key_i );
344 344
         d0 := pc1_d( key_i );
345
-      END IF;
346
-    END PROCESS crypt;
345
+      end if;
346
+    end process crypt;
347 347
 
348 348
   end generate PipeG;
349 349
 
@@ -358,7 +358,6 @@ begin
358 358
 
359 359
   begin
360 360
 
361
-
362 361
     cryptP : process (clk_i, reset_i) is
363 362
       variable v_c       : std_logic_vector(0 to 27);
364 363
       variable v_d       : std_logic_vector(0 to 27);
@@ -624,5 +623,4 @@ begin
624 623
   end generate AreaG;
625 624
 
626 625
 
627
-
628
-END ARCHITECTURE rtl;
626
+end architecture rtl;

+ 109
- 199
des/rtl/vhdl/des_pkg.vhd View File

@@ -20,37 +20,16 @@
20 20
 
21 21
 
22 22
 
23
-LIBRARY ieee;
24
-USE ieee.std_logic_1164.all;
25
-USE ieee.numeric_std.ALL;
23
+library ieee;
24
+  use ieee.std_logic_1164.all;
25
+  use ieee.numeric_std.all;
26 26
 
27 27
 
28 28
 
29
-PACKAGE des_pkg IS
29
+package des_pkg is
30 30
 
31 31
 
32
-  FUNCTION ip  ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
33
-  FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
34
-
35
-  FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector;
36
-  FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector;
37
-
38
-  FUNCTION s1 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
39
-  FUNCTION s2 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
40
-  FUNCTION s3 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
41
-  FUNCTION s4 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
42
-  FUNCTION s5 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
43
-  FUNCTION s6 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
44
-  FUNCTION s7 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
45
-  FUNCTION s8 (input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector;
46
-
47
-  FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector;
48
-
49
-  FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
50
-  FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector;
51
-  FUNCTION pc2   ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector;
52
-
53
-  TYPE ip_matrix IS ARRAY (0 TO 63) OF natural RANGE 0 TO 63;
32
+  type ip_matrix is array (0 to 63) of natural range 0 to 63;
54 33
   constant ip_table : ip_matrix := (57, 49, 41, 33, 25, 17,  9, 1,
55 34
                                 59, 51, 43, 35, 27, 19, 11, 3,
56 35
                                 61, 53, 45, 37, 29, 21, 13, 5,
@@ -68,7 +47,7 @@ PACKAGE des_pkg IS
68 47
                                 33,  1, 41,  9, 49, 17, 57, 25,
69 48
                                 32,  0, 40,  8, 48, 16, 56, 24);
70 49
 
71
-  TYPE e_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 31;
50
+  type e_matrix is array (0 to 47) of natural range 0 to 31;
72 51
   constant e_table : e_matrix := (31,  0,  1,  2,  3,  4,
73 52
                                  3,  4,  5,  6,  7,  8,
74 53
                                  7,  8,  9, 10, 11, 12,
@@ -78,7 +57,7 @@ PACKAGE des_pkg IS
78 57
                                 23, 24, 25, 26, 27, 28,
79 58
                                 27, 28, 29, 30, 31,  0);
80 59
 
81
-  TYPE s_matrix IS ARRAY (0 TO 3, 0 TO 15) OF integer RANGE 0 TO 15;
60
+  type s_matrix is array (0 to 3, 0 to 15) of integer range 0 to 15;
82 61
   constant s1_table  : s_matrix := (0 => (14,  4, 13,  1,  2, 15, 11,  8,  3, 10,  6, 12,  5,  9,  0,  7),
83 62
                                     1 => ( 0, 15,  7,  4, 14,  2, 13,  1, 10,  6, 12, 11,  9,  5,  3,  8),
84 63
                                     2 => ( 4,  1, 14,  8, 13,  6,  2, 11, 15, 12,  9,  7,  3, 10,  5,  0),
@@ -112,7 +91,7 @@ PACKAGE des_pkg IS
112 91
                                     2 => ( 7, 11,  4,  1,  9, 12, 14,  2,  0,  6, 10, 13, 15,  3,  5,  8),
113 92
                                     3 => ( 2,  1, 14,  7,  4, 10,  8, 13, 15, 12,  9,  0,  3,  5,  6, 11));
114 93
 
115
-  type pc_matrix IS ARRAY (0 TO 27) OF natural RANGE 0 TO 63;
94
+  type pc_matrix is array (0 to 27) of natural range 0 to 63;
116 95
   constant pc1c_table : pc_matrix := (56, 48, 40, 32, 24, 16,  8,
117 96
                                  0, 57, 49, 41, 33, 25, 17,
118 97
                                  9,  1, 58, 50, 42, 34, 26,
@@ -122,7 +101,7 @@ PACKAGE des_pkg IS
122 101
                                 13,  5, 60, 52, 44, 36, 28,
123 102
                                 20, 12,  4, 27, 19, 11,  3);
124 103
 
125
-  type p_matrix IS ARRAY (0 TO 31) OF natural RANGE 0 TO 31;
104
+  type p_matrix is array (0 to 31) of natural range 0 to 31;
126 105
   constant p_table : p_matrix := (15,  6, 19, 20,
127 106
                                 28, 11, 27, 16,
128 107
                                  0, 14, 22, 25,
@@ -132,7 +111,7 @@ PACKAGE des_pkg IS
132 111
                                 18, 12, 29,  5,
133 112
                                 21, 10,  3, 24);
134 113
 
135
-  type pc2_matrix IS ARRAY (0 TO 47) OF natural RANGE 0 TO 63;
114
+  type pc2_matrix is array (0 to 47) of natural range 0 to 63;
136 115
   constant pc2_table : pc2_matrix := (13, 16, 10, 23,  0,  4,
137 116
                                  2, 27, 14,  5, 20,  9,
138 117
                                 22, 18, 11,  3, 25,  7,
@@ -142,191 +121,122 @@ PACKAGE des_pkg IS
142 121
                                 43, 48, 38, 55, 33, 52,
143 122
                                 45, 41, 49, 35, 28, 31);
144 123
 
124
+  function ip  ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
125
+  function ipn ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
126
+
127
+  function e (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector;
128
+  function p (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector;
129
+
130
+  function s (input_vector : std_logic_vector(0 to 5); s_table : s_matrix ) return std_logic_vector;
131
+
132
+  function f (input_r : std_logic_vector(0 to 31); input_key : std_logic_vector(0 to 47) ) return std_logic_vector;
133
+
134
+  function pc1_c ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
135
+  function pc1_d ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector;
136
+  function pc2   ( input_vector : std_logic_vector(0 to 55) ) return std_logic_vector;
137
+
145 138
 
146
-END PACKAGE des_pkg;
139
+end package des_pkg;
147 140
 
148 141
 
149 142
 
150
-PACKAGE BODY des_pkg IS
143
+package body des_pkg is
151 144
 
152 145
 
153
-  FUNCTION ip ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
154
-    VARIABLE result : std_logic_vector(0 TO 63);
155
-  BEGIN
156
-    FOR index IN 0 TO 63 LOOP
146
+  function ip ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
147
+    variable result : std_logic_vector(0 to 63);
148
+  begin
149
+    for index IN 0 to 63 loop
157 150
       result( index ) := input_vector( ip_table( index ) );
158
-    END LOOP;
159
-    RETURN result;
160
-  END FUNCTION ip;
161
-
162
-  FUNCTION ipn ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
163
-    VARIABLE result : std_logic_vector(0 TO 63);
164
-  BEGIN
165
-    FOR index IN 0 TO 63 LOOP
151
+    end loop;
152
+    return result;
153
+  end function ip;
154
+
155
+
156
+  function ipn ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
157
+    variable result : std_logic_vector(0 to 63);
158
+  begin
159
+    for index IN 0 to 63 loop
166 160
       result( index ) := input_vector( ipn_table( index ) );
167
-    END LOOP;
168
-    RETURN result;
169
-  END FUNCTION ipn;
170
-
171
-  FUNCTION e (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS
172
-    VARIABLE result : std_logic_vector(0 TO 47);
173
-  BEGIN
174
-    FOR index IN 0 TO 47 LOOP
161
+    end loop;
162
+    return result;
163
+  end function ipn;
164
+
165
+
166
+  function e (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector is
167
+    variable result : std_logic_vector(0 to 47);
168
+  begin
169
+    for index IN 0 to 47 loop
175 170
       result( index ) := input_vector( e_table( index ) );
176
-    END LOOP;
177
-    RETURN result;
178
-  END FUNCTION e;
179
-
180
-  FUNCTION s1 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
181
-    VARIABLE int : std_logic_vector(0 TO 1);
182
-    VARIABLE i : integer RANGE 0 TO 3;
183
-    VARIABLE j : integer RANGE 0 TO 15;
184
-    VARIABLE result : std_logic_vector(0 TO 3);
185
-  BEGIN
186
-    int := input_vector( 0 ) & input_vector( 5 );
187
-    i := to_integer( unsigned( int ) );
188
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
189
-    result := std_logic_vector( to_unsigned( s1_table( i, j ), 4 ) );
190
-    RETURN result;
191
-  END FUNCTION s1;
192
-
193
-  FUNCTION s2 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
194
-    VARIABLE int : std_logic_vector(0 TO 1);
195
-    VARIABLE i : integer RANGE 0 TO 3;
196
-    VARIABLE j : integer RANGE 0 TO 15;
197
-    VARIABLE result : std_logic_vector(0 TO 3);
198
-  BEGIN
199
-    int := input_vector( 0 ) & input_vector( 5 );
200
-    i := to_integer( unsigned( int ) );
201
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
202
-    result := std_logic_vector( to_unsigned( s2_table( i, j ), 4 ) );
203
-    RETURN result;
204
-  END FUNCTION s2;
205
-
206
-  FUNCTION s3 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
207
-    VARIABLE int : std_logic_vector(0 TO 1);
208
-    VARIABLE i : integer RANGE 0 TO 3;
209
-    VARIABLE j : integer RANGE 0 TO 15;
210
-    VARIABLE result : std_logic_vector(0 TO 3);
211
-  BEGIN
212
-    int := input_vector( 0 ) & input_vector( 5 );
213
-    i := to_integer( unsigned( int ) );
214
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
215
-    result := std_logic_vector( to_unsigned( s3_table( i, j ), 4 ) );
216
-    RETURN result;
217
-  END FUNCTION s3;
218
-
219
-  FUNCTION s4 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
220
-    VARIABLE int : std_logic_vector(0 TO 1);
221
-    VARIABLE i : integer RANGE 0 TO 3;
222
-    VARIABLE j : integer RANGE 0 TO 15;
223
-    VARIABLE result : std_logic_vector(0 TO 3);
224
-  BEGIN
225
-    int := input_vector( 0 ) & input_vector( 5 );
226
-    i := to_integer( unsigned( int ) );
227
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
228
-    result := std_logic_vector( to_unsigned( s4_table( i, j ), 4 ) );
229
-    RETURN result;
230
-  END FUNCTION s4;
231
-
232
-  FUNCTION s5 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
233
-    VARIABLE int : std_logic_vector(0 TO 1);
234
-    VARIABLE i : integer RANGE 0 TO 3;
235
-    VARIABLE j : integer RANGE 0 TO 15;
236
-    VARIABLE result : std_logic_vector(0 TO 3);
237
-  BEGIN
238
-    int := input_vector( 0 ) & input_vector( 5 );
239
-    i := to_integer( unsigned( int ) );
240
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
241
-    result := std_logic_vector( to_unsigned( s5_table( i, j ), 4 ) );
242
-    RETURN result;
243
-  END FUNCTION s5;
244
-
245
-  FUNCTION s6 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
246
-    VARIABLE int : std_logic_vector(0 TO 1);
247
-    VARIABLE i : integer RANGE 0 TO 3;
248
-    VARIABLE j : integer RANGE 0 TO 15;
249
-    VARIABLE result : std_logic_vector(0 TO 3);
250
-  BEGIN
251
-    int := input_vector( 0 ) & input_vector( 5 );
252
-    i := to_integer( unsigned( int ) );
253
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
254
-    result := std_logic_vector( to_unsigned( s6_table( i, j ), 4 ) );
255
-    RETURN result;
256
-  END FUNCTION s6;
257
-
258
-  FUNCTION s7 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
259
-    VARIABLE int : std_logic_vector(0 TO 1);
260
-    VARIABLE i : integer RANGE 0 TO 3;
261
-    VARIABLE j : integer RANGE 0 TO 15;
262
-    VARIABLE result : std_logic_vector(0 TO 3);
263
-  BEGIN
264
-    int := input_vector( 0 ) & input_vector( 5 );
265
-    i := to_integer( unsigned( int ) );
266
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
267
-    result := std_logic_vector( to_unsigned( s7_table( i, j ), 4 ) );
268
-    RETURN result;
269
-  END FUNCTION s7;
270
-
271
-  FUNCTION s8 ( input_vector : std_logic_vector(0 TO 5) ) RETURN std_logic_vector IS
272
-    VARIABLE int : std_logic_vector(0 TO 1);
273
-    VARIABLE i : integer RANGE 0 TO 3;
274
-    VARIABLE j : integer RANGE 0 TO 15;
275
-    VARIABLE result : std_logic_vector(0 TO 3);
276
-  BEGIN
171
+    end loop;
172
+    return result;
173
+  end function e;
174
+
175
+
176
+  function s ( input_vector : std_logic_vector(0 to 5); s_table : s_matrix ) return std_logic_vector is
177
+    variable int : std_logic_vector(0 to 1);
178
+    variable i : integer range 0 to 3;
179
+    variable j : integer range 0 to 15;
180
+    variable result : std_logic_vector(0 to 3);
181
+  begin
277 182
     int := input_vector( 0 ) & input_vector( 5 );
278 183
     i := to_integer( unsigned( int ) );
279
-    j := to_integer( unsigned( input_vector( 1 TO 4) ) );
280
-    result := std_logic_vector( to_unsigned( s8_table( i, j ), 4 ) );
281
-    RETURN result;
282
-  END FUNCTION s8;
283
-
284
-  FUNCTION p (input_vector : std_logic_vector(0 TO 31) ) RETURN std_logic_vector IS
285
-    VARIABLE result : std_logic_vector(0 TO 31);
286
-  BEGIN
287
-    FOR index IN 0 TO 31 LOOP
184
+    j := to_integer( unsigned( input_vector( 1 to 4) ) );
185
+    result := std_logic_vector( to_unsigned( s_table( i, j ), 4 ) );
186
+    return result;
187
+  end function s;
188
+
189
+
190
+  function p (input_vector : std_logic_vector(0 to 31) ) return std_logic_vector is
191
+    variable result : std_logic_vector(0 to 31);
192
+  begin
193
+    for index IN 0 to 31 loop
288 194
       result( index ) := input_vector( p_table( index ) );
289
-    END LOOP;
290
-    RETURN result;
291
-  END FUNCTION p;
292
-
293
-  FUNCTION f (input_r : std_logic_vector(0 TO 31); input_key : std_logic_vector(0 TO 47) ) RETURN std_logic_vector IS
294
-    VARIABLE intern : std_logic_vector(0 TO 47);
295
-    VARIABLE result : std_logic_vector(0 TO 31);
296
-  BEGIN
195
+    end loop;
196
+    return result;
197
+  end function p;
198
+
199
+
200
+  function f (input_r : std_logic_vector(0 to 31); input_key : std_logic_vector(0 to 47) ) return std_logic_vector is
201
+    variable intern : std_logic_vector(0 to 47);
202
+    variable result : std_logic_vector(0 to 31);
203
+  begin
297 204
     intern := e( input_r ) xor input_key;
298
-    result := p( s1( intern(0 TO 5) ) & s2( intern(6 TO 11) ) & s3( intern(12 TO 17) ) & s4( intern(18 TO 23) ) &
299
-              s5( intern(24 TO 29) ) & s6( intern(30 TO 35) ) & s7( intern(36 TO 41) ) & s8( intern(42 TO 47) ) );
300
-    RETURN result;
301
-  END FUNCTION f;
302
-
303
-  FUNCTION pc1_c ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
304
-    VARIABLE result : std_logic_vector(0 TO 27);
305
-  BEGIN
306
-    FOR index IN 0 TO 27 LOOP
205
+    result := p( s( intern(0 to 5), s1_table )   & s( intern(6 to 11), s2_table )  & s( intern(12 to 17), s3_table ) &
206
+                 s( intern(18 to 23), s4_table ) & s( intern(24 to 29), s5_table ) & s( intern(30 to 35), s6_table ) &
207
+                 s( intern(36 to 41), s7_table ) & s( intern(42 to 47), s8_table ) );
208
+    return result;
209
+  end function f;
210
+
211
+
212
+  function pc1_c ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
213
+    variable result : std_logic_vector(0 to 27);
214
+  begin
215
+    for index IN 0 to 27 loop
307 216
       result( index ) := input_vector( pc1c_table( index ) );
308
-    END LOOP;
309
-    RETURN result;
310
-  END FUNCTION pc1_c;
217
+    end loop;
218
+    return result;
219
+  end function pc1_c;
311 220
 
312
-  FUNCTION pc1_d ( input_vector : std_logic_vector(0 TO 63) ) RETURN std_logic_vector IS
313 221
 
314
-    VARIABLE result : std_logic_vector(0 TO 27);
315
-  BEGIN
316
-    FOR index IN 0 TO 27 LOOP
222
+  function pc1_d ( input_vector : std_logic_vector(0 to 63) ) return std_logic_vector is
223
+    variable result : std_logic_vector(0 to 27);
224
+  begin
225
+    for index IN 0 to 27 loop
317 226
       result( index ) := input_vector( pc1d_table( index ) );
318
-    END LOOP;
319
-    RETURN result;
320
-  END FUNCTION pc1_d;
321
-
322
-  FUNCTION pc2 ( input_vector : std_logic_vector(0 TO 55) ) RETURN std_logic_vector IS
323
-    VARIABLE result : std_logic_vector(0 TO 47);
324
-  BEGIN
325
-    FOR index IN 0 TO 47 LOOP
227
+    end loop;
228
+    return result;
229
+  end function pc1_d;
230
+
231
+
232
+  function pc2 ( input_vector : std_logic_vector(0 to 55) ) return std_logic_vector is
233
+    variable result : std_logic_vector(0 to 47);
234
+  begin
235
+    for index IN 0 to 47 loop
326 236
       result( index ) := input_vector( pc2_table( index ) );
327
-    END LOOP;
328
-    RETURN result;
329
-  END FUNCTION pc2;
237
+    end loop;
238
+    return result;
239
+  end function pc2;
330 240
 
331 241
 
332
-END PACKAGE BODY des_pkg;
242
+end package body des_pkg;