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Add remaining AES functions

* addroundkey()
* subword()
* rotword()
* rcon()
master
T. Meissner 6 years ago
parent
commit
2f91130184
4 changed files with 139 additions and 24 deletions
  1. +43
    -1
      aes/rtl/vhdl/aes.vhd
  2. +81
    -18
      aes/rtl/vhdl/aes_pkg.vhd
  3. +7
    -3
      aes/sim/vhdl/makefile
  4. +8
    -2
      aes/sim/vhdl/tb_aes.vhd

+ 43
- 1
aes/rtl/vhdl/aes.vhd View File

@ -35,8 +35,10 @@ entity aes is
key_i : in std_logic_vector(0 TO 127); -- key input
data_i : in std_logic_vector(0 TO 127); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic;
data_o : out std_logic_vector(0 TO 127); -- data output
valid_o : out std_logic -- output data valid flag
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic
);
end entity aes;
@ -45,7 +47,47 @@ end entity aes;
architecture rtl of aes is
signal s_fsm_state : t_rounds;
signal s_aes_state : t_datatable2d;
signal s_accept : std_logic;
signal s_key_sched_done : boolean;
begin
KeySchedP : process (reset_i, clk_i) is
begin
end process KeySchedP;
AesIter: process (reset_i, clk_i) is
variable v_mode : std_logic;
variable v_round_cnt : t_rounds;
variable v_key : t_key;
begin
if(reset_i = '0') then
s_accept <= '1';
data_o <= (others => '0');
valid_o <= '0';
v_mode := '0';
v_key := (others => (others => '0'));
v_round_cnt := t_rounds'low;
elsif rising_edge(clk_i) then
FsmC : case s_fsm_state is
when 0 =>
if(s_accept = '1' and valid_i = '1') then
v_mode := mode_i;
end if;
end case FsmC;
end if;
end process AesIter;
accept_o <= s_accept;
end architecture rtl;

+ 81
- 18
aes/rtl/vhdl/aes_pkg.vhd View File

@ -18,22 +18,37 @@
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
-- aes implementation
-- key length: 128 bit -> Nk = 4
-- data width: 128 bit -> Nb = 4
-- round number Nr = 10
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package aes_pkg is
-- constants for AES128
constant c_nk : natural := 4; -- key size
constant c_nb : natural := 4; -- number of bytes
constant c_nr : natural := 10; -- number of rounds
subtype t_rounds is natural range 0 to c_nr + 1;
subtype t_key_rounds is natural range c_nk to c_nb * (c_nr + 1);
type t_datatable1d is array (0 to 3) of std_logic_vector(7 downto 0);
type t_datatable2d is array (0 to 3) of t_datatable1d;
type t_stable1d is array (0 to 15) of std_logic_vector(7 downto 0);
type t_stable2d is array (0 to 15) of t_stable1d;
type t_key is array (0 to 3) of std_logic_vector(31 downto 0);
constant c_sbox : t_stable2d := (
-- 0 1 2 3 4 5 6 7 8 9 A B C D E F
(x"63", x"7c", x"77", x"7b", x"f2", x"6b", x"6f", x"c5", x"30", x"01", x"67", x"2b", x"fe", x"d7", x"ab", x"76"), -- 0
@ -85,7 +100,13 @@ package aes_pkg is
function gmul (a : std_logic_vector(7 downto 0); b : std_logic_vector(7 downto 0)) return std_logic_vector;
--function addroundkey (data : in std_logic_vector(127 downto 0), key )
function addroundkey (input : in t_datatable2d; key : in t_key) return t_datatable2d;
function subword (input : in t_datatable1d) return t_datatable1d;
function rotword (input : in t_datatable1d) return t_datatable1d;
function rcon (round : in t_rounds) return t_datatable1d;
end package aes_pkg;
@ -161,23 +182,27 @@ package body aes_pkg is
-- algorithmus in c taken from http://www.samiam.org/galois.html and rewritten in vhdl
function gmul (a : std_logic_vector(7 downto 0); b : std_logic_vector(7 downto 0)) return std_logic_vector is
variable v_a, v_b : std_logic_vector(7 downto 0);
variable v_data : std_logic_vector(7 downto 0) := (others => '0');
--variable v_data : std_logic_vector(7 downto 0) := (others => '0');
variable v_hi_bit_set : std_logic := '0';
variable v_data : unsigned(15 downto 0);
begin
v_a := a;
v_b := b;
for index in 0 to 7 loop
if(v_b(0) = '1') then
v_data := v_data xor v_a;
end if;
v_hi_bit_set := a(7);
v_a := v_a(6 downto 0) & '0';
if(v_hi_bit_set = '1') then
v_a := v_a xor x"01";
end if;
v_b := '0' & v_b(7 downto 1);
end loop;
return v_data;
--v_a := a;
--v_b := b;
--for index in 0 to 7 loop
-- if(v_b(0) = '1') then
-- v_data := v_data xor v_a;
-- end if;
-- v_hi_bit_set := a(7);
-- v_a := v_a(6 downto 0) & '0';
-- if(v_hi_bit_set = '1') then
-- v_a := v_a xor x"01";
-- end if;
-- v_b := '0' & v_b(7 downto 1);
--end loop;
--return v_data;
v_data := unsigned(a) * unsigned(b);
return std_logic_vector(v_data(7 downto 0));
--return std_logic_vector((unsigned(a) * unsigned(b)) (7 downto 0)); -- mod a'length);
end function gmul;
@ -195,4 +220,42 @@ package body aes_pkg is
end function mixcolumns;
function addroundkey (input : in t_datatable2d; key : in t_key) return t_datatable2d is
variable v_data : t_datatable2d;
variable v_key : t_datatable1d;
begin
for i in 0 to 2 loop
v_key := (key(i)(7 downto 0), key(i)(15 downto 8), key(i)(23 downto 16), key(i)(31 downto 24));
for j in 0 to 3 loop
v_data(i)(j) := input(i)(j) xor v_key(j);
end loop;
end loop;
return v_data;
end function addroundkey;
function subword (input : in t_datatable1d) return t_datatable1d is
variable v_data : t_datatable1d;
begin
for i in 0 to 3 loop
v_data(i) := c_sbox(to_integer(unsigned(input(i)(7 downto 4))))(to_integer(unsigned(input(i)(3 downto 0))));
end loop;
return v_data;
end function subword;
function rotword (input : in t_datatable1d) return t_datatable1d is
begin
return(input(2), input(1), input(0), input(3));
end function rotword;
function rcon (round : in t_rounds) return t_datatable1d is
variable v_data : std_logic_vector(15 downto 0);
begin
v_data := std_logic_vector(to_unsigned(2**(round-1), 15));
return(v_data(7 downto 0), x"00", x"00", x"00");
end function rcon;
end package body aes_pkg;

+ 7
- 3
aes/sim/vhdl/makefile View File

@ -23,15 +23,19 @@ all : sim wave
sim : tb_aes.ghw
tb_aes.ghw : ../../rtl/vhdl/*.vhd tb_aes.vhd
compile : ../../rtl/vhdl/*.vhd tb_aes.vhd
ghdl -a ../../rtl/vhdl/aes_pkg.vhd ../../rtl/vhdl/aes.vhd tb_aes.vhd
ghdl -e tb_aes
tb_aes.ghw : compile
ghdl -r tb_aes --wave=tb_aes.ghw --assert-level=error --stop-time=10us
wave : tb_aes.ghw
gtkwave -S tb_aes.tcl tb_aes.ghw
clean :
echo "# cleaning simulation files"
rm -f tb_aes
rm -f tb_aes.ghw
rm -f *.cf
rm -f *.o

+ 8
- 2
aes/sim/vhdl/tb_aes.vhd View File

@ -42,8 +42,10 @@ architecture rtl of tb_aes is
signal s_key : std_logic_vector(0 to 127) := (others => '0');
signal s_datain : std_logic_vector(0 to 127) := (others => '0');
signal s_validin : std_logic := '0';
signal s_acceptout : std_logic;
signal s_dataout : std_logic_vector(0 to 127);
signal s_validout : std_logic;
signal s_acceptin : std_logic;
component aes is
@ -54,8 +56,10 @@ architecture rtl of tb_aes is
key_i : in std_logic_vector(0 TO 127);
data_i : in std_logic_vector(0 TO 127);
valid_i : in std_logic;
accept_o : out std_logic;
data_o : out std_logic_vector(0 TO 127);
valid_o : out std_logic
valid_o : out std_logic;
accept_i : in std_logic
);
end component aes;
@ -162,8 +166,10 @@ begin
key_i => s_key,
data_i => s_datain,
valid_i => s_validin,
accept_o => s_acceptout,
data_o => s_dataout,
valid_o => s_validout
valid_o => s_validout,
accept_i => s_acceptin
);


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