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Add remaining AES functions

* addroundkey()
* subword()
* rotword()
* rcon()
T. Meissner 3 years ago
parent
commit
2f91130184
4 changed files with 139 additions and 24 deletions
  1. 43
    1
      aes/rtl/vhdl/aes.vhd
  2. 81
    18
      aes/rtl/vhdl/aes_pkg.vhd
  3. 7
    3
      aes/sim/vhdl/makefile
  4. 8
    2
      aes/sim/vhdl/tb_aes.vhd

+ 43
- 1
aes/rtl/vhdl/aes.vhd View File

@@ -35,8 +35,10 @@ entity aes is
35 35
     key_i       : in  std_logic_vector(0 TO 127);  -- key input
36 36
     data_i      : in  std_logic_vector(0 TO 127);  -- data input
37 37
     valid_i     : in  std_logic;                   -- input key/data valid flag
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+    accept_o    : out std_logic;
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     data_o      : out std_logic_vector(0 TO 127);  -- data output
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-    valid_o     : out std_logic                    -- output data valid flag
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+    valid_o     : out std_logic;                   -- output data valid flag
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+    accept_i    : in  std_logic
40 42
   );
41 43
 end entity aes;
42 44
 
@@ -45,7 +47,47 @@ end entity aes;
45 47
 architecture rtl of aes is
46 48
 
47 49
 
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+  signal s_fsm_state : t_rounds;
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+  signal s_aes_state : t_datatable2d;
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+  signal s_accept : std_logic;
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+  signal s_key_sched_done : boolean;
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+
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+
48 56
 begin
49 57
 
50 58
 
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+  KeySchedP : process (reset_i, clk_i) is
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+  begin
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+
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+  end process KeySchedP;
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+
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+
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+  AesIter: process (reset_i, clk_i) is
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+    variable v_mode      : std_logic;
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+    variable v_round_cnt : t_rounds;
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+    variable v_key       : t_key;
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+  begin
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+    if(reset_i = '0') then
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+      s_accept    <= '1';
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+      data_o      <= (others => '0');
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+      valid_o     <= '0';
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+      v_mode      := '0';
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+      v_key       := (others => (others => '0'));
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+      v_round_cnt := t_rounds'low;
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+    elsif rising_edge(clk_i) then
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+      FsmC : case s_fsm_state is
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+
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+        when 0 =>
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+          if(s_accept = '1' and valid_i = '1') then
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+            v_mode := mode_i;
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+          end if;
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+
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+      end case FsmC;
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+    end if;
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+  end process AesIter;
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+
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+
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+  accept_o <= s_accept;
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+
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+
51 93
 end architecture rtl;

+ 81
- 18
aes/rtl/vhdl/aes_pkg.vhd View File

@@ -18,22 +18,37 @@
18 18
 -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19 19
 -- ======================================================================
20 20
 
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+-- aes implementation
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+-- key length: 128 bit -> Nk = 4
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+-- data width: 128 bit -> Nb = 4
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+-- round number Nr = 10
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+
21 26
 
22 27
 library ieee;
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-use ieee.std_logic_1164.all;
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-use ieee.numeric_std.all;
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+  use ieee.std_logic_1164.all;
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+  use ieee.numeric_std.all;
25 30
 
26 31
 
27 32
 
28 33
 package aes_pkg is
29 34
 
30 35
 
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+  -- constants for AES128
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+  constant c_nk : natural := 4;   -- key size
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+  constant c_nb : natural := 4;   -- number of bytes
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+  constant c_nr : natural := 10;  -- number of rounds
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+
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+  subtype t_rounds is natural range 0 to c_nr + 1;
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+  subtype t_key_rounds is natural range c_nk to c_nb * (c_nr + 1);
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+
31 44
   type t_datatable1d is array (0 to 3) of std_logic_vector(7 downto 0);
32 45
   type t_datatable2d is array (0 to 3) of t_datatable1d;
33 46
 
34 47
   type t_stable1d is array (0 to 15) of std_logic_vector(7 downto 0);
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   type t_stable2d is array (0 to 15) of t_stable1d;
36 49
 
50
+  type t_key is array (0 to 3) of std_logic_vector(31 downto 0);
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+
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   constant c_sbox : t_stable2d := (
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     -- 0     1      2      3      4      5      6      7      8      9      A      B      C      D      E      F
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     (x"63", x"7c", x"77", x"7b", x"f2", x"6b", x"6f", x"c5", x"30", x"01", x"67", x"2b", x"fe", x"d7", x"ab", x"76"), -- 0
@@ -85,7 +100,13 @@ package aes_pkg is
85 100
 
86 101
   function gmul (a : std_logic_vector(7 downto 0); b : std_logic_vector(7 downto 0)) return std_logic_vector;
87 102
 
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-  --function addroundkey (data : in std_logic_vector(127 downto 0), key )
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+  function addroundkey (input : in t_datatable2d; key : in t_key) return t_datatable2d;
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+
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+  function subword (input : in t_datatable1d) return t_datatable1d;
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+
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+  function rotword (input : in t_datatable1d) return t_datatable1d;
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+
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+  function rcon (round : in t_rounds) return t_datatable1d;
89 110
 
90 111
 
91 112
 end package aes_pkg;
@@ -161,23 +182,27 @@ package body aes_pkg is
161 182
   -- algorithmus in c taken from http://www.samiam.org/galois.html and rewritten in vhdl
162 183
   function gmul (a : std_logic_vector(7 downto 0); b : std_logic_vector(7 downto 0)) return std_logic_vector is
163 184
     variable v_a, v_b     : std_logic_vector(7 downto 0);
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-    variable v_data       : std_logic_vector(7 downto 0) := (others => '0');
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+    --variable v_data       : std_logic_vector(7 downto 0) := (others => '0');
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     variable v_hi_bit_set : std_logic := '0';
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+    variable v_data : unsigned(15 downto 0);
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   begin
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-    v_a := a;
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-    v_b := b;
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-    for index in 0 to 7 loop
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-      if(v_b(0) = '1') then
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-        v_data := v_data xor v_a;
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-      end if;
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-      v_hi_bit_set := a(7);
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-      v_a          := v_a(6 downto 0) & '0';
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-      if(v_hi_bit_set = '1') then
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-        v_a := v_a xor x"01";
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-      end if;
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-      v_b := '0' & v_b(7 downto 1);
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-    end loop;
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-    return v_data;
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+    --v_a := a;
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+    --v_b := b;
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+    --for index in 0 to 7 loop
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+    --  if(v_b(0) = '1') then
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+    --    v_data := v_data xor v_a;
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+    --  end if;
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+    --  v_hi_bit_set := a(7);
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+    --  v_a          := v_a(6 downto 0) & '0';
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+    --  if(v_hi_bit_set = '1') then
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+    --    v_a := v_a xor x"01";
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+    --  end if;
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+    --  v_b := '0' & v_b(7 downto 1);
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+    --end loop;
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+    --return v_data;
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+    v_data := unsigned(a) * unsigned(b);
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+    return std_logic_vector(v_data(7 downto 0));
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+    --return std_logic_vector((unsigned(a) * unsigned(b)) (7 downto 0));  -- mod a'length);
181 206
   end function gmul;
182 207
 
183 208
 
@@ -195,4 +220,42 @@ package body aes_pkg is
195 220
   end function mixcolumns;
196 221
 
197 222
 
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+  function addroundkey (input : in t_datatable2d; key : in t_key) return t_datatable2d is
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+    variable v_data : t_datatable2d;
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+    variable v_key  : t_datatable1d;
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+  begin
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+    for i in 0 to 2 loop
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+      v_key := (key(i)(7 downto 0), key(i)(15 downto 8), key(i)(23 downto 16), key(i)(31 downto 24));
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+      for j in 0 to 3 loop
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+        v_data(i)(j) := input(i)(j) xor v_key(j);
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+      end loop;
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+    end loop;
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+    return v_data;
234
+  end function addroundkey;
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+
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+
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+  function subword (input : in t_datatable1d) return t_datatable1d is
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+    variable v_data : t_datatable1d;
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+  begin
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+    for i in 0 to 3 loop
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+      v_data(i) := c_sbox(to_integer(unsigned(input(i)(7 downto 4))))(to_integer(unsigned(input(i)(3 downto 0))));
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+    end loop;
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+    return v_data;
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+  end function subword;
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+
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+
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+  function rotword (input : in t_datatable1d) return t_datatable1d is
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+  begin
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+    return(input(2), input(1), input(0), input(3));
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+  end function rotword;
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+
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+
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+  function rcon (round : in t_rounds) return t_datatable1d is
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+    variable v_data : std_logic_vector(15 downto 0);
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+  begin
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+    v_data := std_logic_vector(to_unsigned(2**(round-1), 15));
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+    return(v_data(7 downto 0), x"00", x"00", x"00");
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+  end function rcon;
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+
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+
198 261
 end package body aes_pkg;

+ 7
- 3
aes/sim/vhdl/makefile View File

@@ -23,15 +23,19 @@ all : sim wave
23 23
 
24 24
 sim : tb_aes.ghw
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-tb_aes.ghw : ../../rtl/vhdl/*.vhd tb_aes.vhd
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+compile : ../../rtl/vhdl/*.vhd tb_aes.vhd
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 	ghdl -a ../../rtl/vhdl/aes_pkg.vhd ../../rtl/vhdl/aes.vhd tb_aes.vhd
28 28
 	ghdl -e tb_aes
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+
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+tb_aes.ghw : compile
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 	ghdl -r tb_aes --wave=tb_aes.ghw --assert-level=error --stop-time=10us
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-	
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+
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 wave : tb_aes.ghw
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 	gtkwave -S tb_aes.tcl tb_aes.ghw
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-	
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+
34 36
 clean :
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 	echo "# cleaning simulation files"
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+	rm -f tb_aes
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 	rm -f tb_aes.ghw
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 	rm -f *.cf
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+	rm -f *.o

+ 8
- 2
aes/sim/vhdl/tb_aes.vhd View File

@@ -42,8 +42,10 @@ architecture rtl of tb_aes is
42 42
   signal s_key      : std_logic_vector(0 to 127) := (others => '0');
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   signal s_datain   : std_logic_vector(0 to 127) := (others => '0');
44 44
   signal s_validin  : std_logic := '0';
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+  signal s_acceptout : std_logic;
45 46
   signal s_dataout  : std_logic_vector(0 to 127);
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   signal s_validout : std_logic;
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+  signal s_acceptin : std_logic;
47 49
 
48 50
 
49 51
   component aes is
@@ -54,8 +56,10 @@ architecture rtl of tb_aes is
54 56
       key_i       : in  std_logic_vector(0 TO 127);
55 57
       data_i      : in  std_logic_vector(0 TO 127);
56 58
       valid_i     : in  std_logic;
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+      accept_o    : out std_logic;
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       data_o      : out std_logic_vector(0 TO 127);
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-      valid_o     : out std_logic
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+      valid_o     : out std_logic;
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+      accept_i    : in  std_logic
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     );
60 64
   end component aes;
61 65
 
@@ -162,8 +166,10 @@ begin
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     key_i    => s_key,
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     data_i   => s_datain,
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     valid_i  => s_validin,
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+    accept_o => s_acceptout,
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     data_o   => s_dataout,
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-    valid_o  => s_validout
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+    valid_o  => s_validout,
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+    accept_i => s_acceptin
167 173
   );
168 174
 
169 175