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93 lines
2.7 KiB
93 lines
2.7 KiB
-- ======================================================================
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-- AES encryption/decryption
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-- algorithm according to FIPS 197 specification
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-- Copyright (C) 2011 Torsten Meissner
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-------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- ======================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.aes_pkg.all;
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entity aes is
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port (
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reset_i : in std_logic; -- async reset
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clk_i : in std_logic; -- clock
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mode_i : in std_logic; -- aes-modus: 0 = encrypt, 1 = decrypt
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key_i : in std_logic_vector(0 TO 127); -- key input
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data_i : in std_logic_vector(0 TO 127); -- data input
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valid_i : in std_logic; -- input key/data valid flag
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accept_o : out std_logic;
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data_o : out std_logic_vector(0 TO 127); -- data output
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valid_o : out std_logic; -- output data valid flag
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accept_i : in std_logic
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);
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end entity aes;
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architecture rtl of aes is
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signal s_fsm_state : t_rounds;
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signal s_aes_state : t_datatable2d;
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signal s_accept : std_logic;
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signal s_key_sched_done : boolean;
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begin
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KeySchedP : process (reset_i, clk_i) is
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begin
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end process KeySchedP;
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AesIter: process (reset_i, clk_i) is
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variable v_mode : std_logic;
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variable v_round_cnt : t_rounds;
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variable v_key : t_key;
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begin
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if(reset_i = '0') then
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s_accept <= '1';
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data_o <= (others => '0');
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valid_o <= '0';
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v_mode := '0';
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v_key := (others => (others => '0'));
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v_round_cnt := t_rounds'low;
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elsif rising_edge(clk_i) then
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FsmC : case s_fsm_state is
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when 0 =>
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if(s_accept = '1' and valid_i = '1') then
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v_mode := mode_i;
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end if;
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end case FsmC;
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end if;
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end process AesIter;
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accept_o <= s_accept;
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end architecture rtl;
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