|
@@ -0,0 +1,7 @@
|
|
1
|
+# cryptocores
|
|
2
|
+cryptography ip-cores in vhdl / verilog
|
|
3
|
+
|
|
4
|
+The components in this repository are not intended for productional code.
|
|
5
|
+They serve as proof of concept, for example how to implement a pipeline using
|
|
6
|
+only (local) variables instead of (global) signals. Furthermore they were used
|
|
7
|
+how to do a VHDL-to-Verilog conversion for learning purposes.
|