Browse Source

Created Readme.md file

master
T. Meissner 5 years ago
committed by GitHub
parent
commit
517237cfec
1 changed files with 7 additions and 0 deletions
  1. +7
    -0
      README.md

+ 7
- 0
README.md View File

@ -0,0 +1,7 @@
# cryptocores
cryptography ip-cores in vhdl / verilog
The components in this repository are not intended for productional code.
They serve as proof of concept, for example how to implement a pipeline using
only (local) variables instead of (global) signals. Furthermore they were used
how to do a VHDL-to-Verilog conversion for learning purposes.

Loading…
Cancel
Save