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cryptography ip-cores in vhdl / verilog
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T. Meissner 517237cfec Created Readme.md file 9 years ago
aes Add remaining AES functions 10 years ago
cbcdes moved array type definitions out of functions to head of package, instances now also in package head and are constants 11 years ago
cbcmac_des merge last changes from amc mini repo 10 years ago
cbctdes removed internal synced copy of reset_i; set ready to high in reset 11 years ago
des merge last changes from amc mini repo 10 years ago
tdes added removing of tb_tdes binary and *.o files in clean target 11 years ago
.gitignore added ignore file 11 years ago
LICENSE.textile added GPLv2 license file 10 years ago
README.md Created Readme.md file 9 years ago

README.md

cryptocores

cryptography ip-cores in vhdl / verilog

The components in this repository are not intended for productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.