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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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223
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1
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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master
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cryptocores
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aes
/
sim
/
vhdl
History
umarcor
6ebfd4afe7
aes: fix build arg order
4 years ago
..
Makefile
aes: fix build arg order
4 years ago
tb_aes.c
Use co-sim for descryption tests also
4 years ago
tb_aes.tcl
Use co-sim for descryption tests also
4 years ago
tb_aes.vhd
Implement key schedule for AES decryption, unoptimized
4 years ago