cryptography ip-cores in vhdl / verilog
vhdl
osvvm
fpga
ghdl
testbenches
verilog
cryptography
T. Meissner b59791e8f3 Move VHDL library files in work directory 10 months ago
aes Move VHDL library files in work directory 10 months ago
cbcdes moved array type definitions out of functions to head of package, instances now also in package head and are constants 6 years ago
cbcmac_des merge last changes from amc mini repo 4 years ago
cbctdes removed internal synced copy of reset_i; set ready to high in reset 5 years ago
des merge last changes from amc mini repo 4 years ago
tdes added removing of tb_tdes binary and *.o files in clean target 5 years ago
.gitignore added ignore file 6 years ago
LICENSE.textile added GPLv2 license file 4 years ago
README.md Created Readme.md file 3 years ago

README.md

cryptocores

cryptography ip-cores in vhdl / verilog

The components in this repository are not intended for productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.