cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
T. Meissner b602931174 Fix CTR-init round, set of iv & key in 1st round only. 1 month ago
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rtl/vhdl CTR-AES: Fix counter incr & init; add 1st simple testbench 1 month ago
sim/vhdl Fix CTR-init round, set of iv & key in 1st round only. 1 month ago
syn/vhdl Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 6 months ago