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cryptography ip-cores in vhdl / verilog
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cryptocores/ctraes
T. Meissner 2a3fae594f Refactor conditions in counter process; add info about submodule update 3 years ago
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rtl/vhdl Refactor conditions in counter process; add info about submodule update 3 years ago
sim/vhdl Fix CTR-init round, set of iv & key in 1st round only. 3 years ago
syn/vhdl Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 years ago