cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
T. Meissner a2c530928e Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 2 weeks ago
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rtl/vhdl Add CBCMAC-AES VHDL design 1 month ago
syn/vhdl Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 2 weeks ago