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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
219
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cryptocores
/
des
T. Meissner
81df6e0215
Update & restructure DES testbench to use openSSL and random simuli
2 weeks ago
..
rtl
Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring
6 months ago
sim
Update & restructure DES testbench to use openSSL and random simuli
2 weeks ago
syn/
vhdl
Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring
6 months ago