* Add functional coverage for block & rmw cycles * Add some more checks for WB rules * Add tests of block cycles
|3 months ago|
|wishbone||3 months ago|
|LICENSE.md||3 months ago|
|README.md||3 months ago|
The original repository is now located on my own git-server at https://git.goodcleanfun.de/tmeissner/verification_ip It is mirrored to github with every push, so both should be in sync.
The components in this repository are not intended as productional code. They are created out of personal interest and to find out what one can achieve with current state of open source tools, expecially in the VHDL domain.
Simple VIP for the wishbone bus protocol. First goal is functional coverage to detect valid transfer cycles and their variants. Currently support of classic single read / write cycles only.