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T. Meissner dbfe16af59 Add more checks, coverage & tests 3 months ago
wishbone Add more checks, coverage & tests 3 months ago Add license text 3 months ago README:clarify project focus & intention 3 months ago

The original repository is now located on my own git-server at It is mirrored to github with every push, so both should be in sync.


Verification IPs for simulation & formal verification of various selected protocols. All tests are done with GHDL and SymbiYosys, a front-end for formal verification flows based on Yosys.

The components in this repository are not intended as productional code. They are created out of personal interest and to find out what one can achieve with current state of open source tools, expecially in the VHDL domain.


Simple VIP for the wishbone bus protocol. First goal is functional coverage to detect valid transfer cycles and their variants. Currently support of classic single read / write cycles only.