library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity TestDesign is
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port (
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clk : in std_logic;
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resetn : in std_logic;
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sel : in std_logic_vector(1 downto 0);
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we : out std_logic_vector(3 downto 0)
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);
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end entity TestDesign;
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architecture rtl of TestDesign is
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begin
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process (CLK, RESETn) is
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begin
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if (RESETn = '0') then
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we <= (others => '0');
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elsif (rising_edge(CLK)) then
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we(0) <= '0' when sel = "00" else '1';
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we(1) <= '0' when sel = "01" else '1';
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we(2) <= '0' when sel = "10" else '1';
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we(3) <= '0' when sel = "11" else '1';
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end if;
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end process;
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end architecture;
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