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Beauty care

master
T. Meissner 3 years ago
parent
commit
7c3adb4be3
1 changed files with 9 additions and 9 deletions
  1. +9
    -9
      tests/Makefile

+ 9
- 9
tests/Makefile View File

@ -13,6 +13,12 @@ else
TOPLEVEL := ${DUT} TOPLEVEL := ${DUT}
endif endif
# Cocotb related
MODULE := tb_${DUT}
COCOTB_LOG_LEVEL := DEBUG
CUSTOM_COMPILE_DEPS := results
COCOTB_RESULTS_FILE := results/${MODULE}.xml
# Simulator (GHDL) & RTL related # Simulator (GHDL) & RTL related
SIM := ghdl SIM := ghdl
TOPLEVEL_LANG := vhdl TOPLEVEL_LANG := vhdl
@ -22,15 +28,9 @@ VHDL_SOURCES := ${EXT}/libvhdl/syn/*.vhd \
SIM_BUILD := work SIM_BUILD := work
COMPILE_ARGS := --std=08 COMPILE_ARGS := --std=08
SIM_ARGS += \ SIM_ARGS += \
--wave=results/${TOPLEVEL}.ghw \
--psl-report=results/${TOPLEVEL}_psl.json \
--vpi-trace=results/${TOPLEVEL}_vpi.log
# Cocotb related
MODULE := tb_${DUT}
COCOTB_LOG_LEVEL := DEBUG
CUSTOM_COMPILE_DEPS := results
COCOTB_RESULTS_FILE := results/${TOPLEVEL}.xml
--wave=results/${MODULE}.ghw \
--psl-report=results/${MODULE}_psl.json \
--vpi-trace=results/${MODULE}_vpi.log
include $(shell cocotb-config --makefiles)/Makefile.sim include $(shell cocotb-config --makefiles)/Makefile.sim


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