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Separate uart tx & rx tests into own testbenches

master
T. Meissner 3 years ago
parent
commit
f42ca7250a
3 changed files with 60 additions and 58 deletions
  1. +10
    -14
      tests/Makefile
  2. +0
    -44
      tests/tb_uartrx.py
  3. +50
    -0
      tests/tb_uarttx.py

+ 10
- 14
tests/Makefile View File

@ -1,29 +1,25 @@
# Default test
DUT ?= uarttx
# Test related variables
ifeq (${DUT}, uarttx)
MODULE := tb_uart
TOPLEVEL := ${DUT}
else ifeq (${DUT}, uartrx)
MODULE := tb_uart
TOPLEVEL := ${DUT}
else ifeq (${DUT}, wishbone)
MODULE := tb_wishbone
ifeq (${DUT}, wishbone)
TOPLEVEL := wishboneslavee
SIM_ARGS := -gSimulation=true \
-gAddressWidth=8 \
-gDataWidth=16
else
$(error ${DUT} not available)
TOPLEVEL := ${DUT}
endif
# Simulator (GHDL) & RTL related
SIM := ghdl
TOPLEVEL_LANG := vhdl
VHDL_SOURCES_libvhdl := ../libvhdl/common/UtilsP.vhd
VHDL_SOURCES := ../libvhdl/syn/*.vhd
VHDL_SOURCES_libvhdl := ../libvhdl/common/UtilsP.vhd
VHDL_SOURCES := ../libvhdl/syn/*.vhd \
../cryptocores/aes/rtl/vhdl/*.vhd
SIM_BUILD := work
COMPILE_ARGS := --std=08
SIM_ARGS += \
@ -32,7 +28,7 @@ SIM_ARGS += \
--vpi-trace=results/${TOPLEVEL}_vpi.log
# Cocotb related
TESTCASE := test_${DUT}
MODULE := tb_${DUT}
COCOTB_LOG_LEVEL := DEBUG
CUSTOM_COMPILE_DEPS := results
COCOTB_RESULTS_FILE := results/${TOPLEVEL}.xml
@ -47,4 +43,4 @@ results:
.PHONY: clean
clean::
rm -rf *.o __pycache__ uarttx uartrx wishboneslavee results
rm -rf *.o __pycache__ uarttx uartrx wishboneslavee aes results

tests/tb_uart.py → tests/tb_uartrx.py View File


+ 50
- 0
tests/tb_uarttx.py View File

@ -0,0 +1,50 @@
import logging
import random
import cocotb
import wavedrom
from Uart import UartDriver, UartReceiver
from Vai import VaiDriver, VaiReceiver
from cocotb.clock import Clock
from cocotb.triggers import FallingEdge, RisingEdge, Timer, ReadOnly
# Reset coroutine
async def reset_dut(reset_n, duration_ns):
reset_n.value = 0
await Timer(duration_ns, units="ns")
reset_n.value = 1
@cocotb.test()
async def test_uarttx(dut):
""" First simple test """
clkedge = RisingEdge(dut.clk_i)
# Connect reset
reset_n = dut.reset_n_i
# Instantiate VAI driver
vai_driver = VaiDriver(dut.clk_i, dut.data_i, dut.valid_i, dut.accept_o)
# Instantiate UART receiver
uart_receiver = UartReceiver(dut.tx_o, dut.clk_i, 10, 8, True);
# Drive input defaults (setimmediatevalue to avoid x asserts)
dut.data_i.setimmediatevalue(0)
dut.valid_i.setimmediatevalue(0)
clock = Clock(dut.clk_i, 10, units="ns") # Create a 10 ns period clock
cocotb.start_soon(clock.start()) # Start the clock
# Execution will block until reset_dut has completed
dut._log.info("Hold reset")
await reset_dut(reset_n, 100)
dut._log.info("Released reset")
# Test 10 UART transmissions
for i in range(10):
await clkedge
val = random.randint(0, 255)
await vai_driver.send(val)
rec = await uart_receiver.receive();
assert rec == val, "UART sent data was incorrect on the {}th cycle".format(i)

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